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hd404639r series 4-bit single-chip microcomputer rev. 6.0 sept. 1998 description the hd404639r series is a member of the hmcs400-series microcomputers designed to increase program productivity with large-capacity memory. the hd404639r series, completely compatible with the hd404639 series, reduces current dissipation in half and includes a high-speed version. each microcomputer has a high-precision dual-tone multi frequency (dtmf) generator, four timers, two serial interfaces, voltage comparator, input capture circuit, 32-khz oscillator for clock, and four low-power dissipation modes. the hd404639r series includes 5 chips: the HD404638R and hd40a4638r with 8-kword rom; the hd404639r and hd40a4639r with 16-kword rom; the hd407a4639r with 16-kword prom. hd40a4638r, hd40a4639r, hd407a4639r are high-speed versions (minimum instruction cycle time: 0.5 m s). the hd407a4639r is a prom version ztat ? microcomputer. a program can be written to the prom by a prom writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (the ztat ? version is 27256-compatible.) ztat tm : zero turn around time. ztat is a trademark of hitachi ltd. features 8,192-word 10-bit rom (HD404638R, hd40a4638r) 16,384-word 10-bit rom (hd404639r, hd40a4639r, hd407a4639r) 1,152-digit 4-bit ram 61 i/o pins and 7 dedicated input pins ? 12 high-current output pins: eight 15-ma sinks (a maximum of 7 pins can be used at the same time) and four 10-ma sources four timer/counters eight-bit input capture circuit three timer outputs (including two pwm outputs) two event counter inputs (including one double-edge function) two clock-synchronous 8-bit serial interfaces
hd404639r series 2 comparator (4 channels) on-chip dtmf generator: f osc = 400 khz, 800 khz, 2 mhz, 3.58 mhz, 4 mhz, 7.16 mhz, or 8 mhz (7.16 mhz and 8 mhz are only available for hd40a4638r, hd40a4639r and hd407a4639r) built-in oscillators ? main clock: ceramic oscillator or crystal (an external clock is also possible) ? subclock: 32.768-khz crystal eleven interrupt sources ? five by external sources, including three double-edge function ? six by internal sources subroutine stack up to 16 levels, including interrupts four low-power dissipation modes ? subactive mode ? standby mode ? watch mode ? stop mode one external input for transition from stop mode to active mode instruction cycle time: 1 m s (f osc = 4 mhz at 1/4 division ratio), 0.5 m s (f osc = 8 mhz at 1/4 division ratio) ? 1/4, 1/8, 1/16, or 1/32 division ratio can be selected operation voltage ? 2.7 v to 6.0 v (HD404638R, hd404639r, hd40a4638r, hd40a4639r) ? 2.7 v to 5.5 v (hd407a4639r) ? with v cc = 2.2 v to 6.0 v, watch mode can be supported, and instructions can be executed in subactive mode (not applicable to the hd407a4639r). two operating modes ? mcu mode ? mcu/prom mode (hd407a4639r) ordering information type instruction cycle time ( m s) product name model name rom (words) package mask rom 1 (f osc = 4 mhz at 1/4 division ratio) HD404638R HD404638Rf 8,192 80-pin plastic qfp (fp-80b) hd404639r hd404639rf 16,384 0.5 (f osc = 8 mhz at1/4 division ratio) hd40a4638r hd40a4638rf 8,192 hd40a4639r hd40a4639rf 16,384 ztat ? 0.5 (f osc = 8 mhz at 1/4 division ratio) hd407a4639r hd407a4639rf 16,384
hd404639r series 3 pin arrangement vt ref 1 2 3 4 8 11 17 18 19 20 21 22 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 2627 2829 303132333435 36373839 40 80 7978 7776 757473727170 69686766 65 r9 r9 r8 r8 r8 r8 r7 r7 r7 r7 r6 r6 r6 r6 5 6 7 9 10 12 13 14 15 16 23 24 v cc (top view) r5 r5 r5 r5 r4 r4 r4 r4 r3 r3 rd /comp rd /comp rd /comp rd /comp osc x2 d d d d d d re /vc test osc reset x1 gnd d d d d d d 0 1 2 3 0 ref 1 2 0 1 2 3 4 5 6 7 8 9 10 11 toner tonec sel rc 0 rb 3 rb 2 rb 1 rb 0 ra 3 ra 2 ra 1 ra 0 r9 3 r9 2 d / stopc 12 d / int r0 / int r0 /int r0 /int r0 /int r1 r1 r1 r1 r2 r2 r2 r2 r3 /tob r3 /toc 13 0 0 1 2 3 1 2 3 4 0 1 2 3 0 1 2 3 0 1 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 /so /si / sck /so /si / sck /evnd / evnb /tod 2 2 2 1 1 1 fp-80b 0 1 2 3
hd404639r series 4 pin description item symbol pin number i/o function power v cc 79 applies power voltage supply gnd 12 connected to ground test test 6 i used for factory testing only: connect this pin to v cc reset reset 9 i resets the mcu oscillator osc 1 7 i input/output pins for the internal oscillator circuit: connect them to a ceramic oscillator, crystal, or connect osc 1 to an external oscillator circuit osc 2 8o x1 10 i used for a 32.768-khz crystal for clock purposes. if not to be used, fix the x1 pin to v cc and leave the x2 pin open. x2 11 o port d 0 ? 11 13?4 i/o input/output pins addressed by individual bits; pins d 4 d 11 are high-current sink pins that can each supply up to 15 ma, d 0 ? 3 are high-current source pins that can each supply up to 10 ma d 12 , d 13 25, 26 i input pins addressable by individual bits r0 0 ?c 0 27?5 i/o input/output pins addressable in 4-bit units rd 0 ?d 3 ,re 0 1? i input pins addressable in 4-bit units interrupt int 0 , int 1 , int 2 ?nt 4 26?0 i input pins for external interrupts stop clear stopc 25 i input pin for transition from stop mode to active mode serial sck 1 , sck 2 44, 48 i/o serial interface clock input/output pin interface si 1 , si 2 45, 49 i serial interface receive data input pin so 1 , so 2 46, 50 o serial interface transmit data output pin timer tob, toc, tod 39?1 o timer output pins evnb , evnd 42, 43 i event count input pins dtmf toner 78 o output pin for dtmf row signals tonec 77 o output pin for dtmf column signals. vt ref 80 reference voltage pin for dtmf signals. voltage conditions being v cc 3 vt ref 3 gnd voltage comparator comp 0 ?omp 3 1? i analog input pins for voltage comparator vc ref 5 reference voltage pin for inputting the threshold voltage of the analog input pin. division rate sel 76 i input pin for selecting system clock division rate after reset input or after stop mode cancellation. 1/4 division rate: connect it to v cc 1/32 division rate: connect it to gnd
hd404639r series 5 block diagram system control external interrupt timer a timer b timer c timer d serial interface 1 serial interface 2 compa- rator dtmf internal data bus internal address bus ram (1,152 4 bit) w (2 bit) x (4 bit) y (4 bit) spx (4 bit) st (1 bit) ca (1 bit) a (4 bit) b (4 bit) sp (10 bit) pc (14 bit) insruction decoder cpu r0 r0 r0 r0 r1 r1 r1 r1 r2 r2 r2 r2 r3 r3 r3 r3 r4 r4 r4 r4 r5 r5 r5 r5 r6 r6 r6 r6 r7 r7 r7 r7 r8 r8 r8 r8 r9 r9 r9 r9 ra ra ra ra rb rb rb rb rd rd rd rd rc re reset test stopc osc osc x1 x2 sel v gnd toc evnd tod int int int int int si so sck vcref comp 0 comp 1 comp 2 comp 3 vtref toner tonec r0 port r1 port r2 port r3 port r4 port rd port 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 0 r5 port r6 port r7 port r8 port r9 port ra port rb port rc port re port si so sck rom (16,384 10 bit) (8,192 10 bit) d port high-current source pins d d d d d d d d d d d d d d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 0 1 2 3 4 evnb tob 1 1 1 2 2 2 high-current sink pins spy (4 bit) alu 1 2 cc
hd404639r series 6 memory map rom memory map the rom memory map is shown in figure 1 and described below. 0 15 16 63 64 4095 4096 16383 0 $000f $0fff $1000 $3fff $0010 $003f $0040 vector address zero-page subroutine (64 words) pattern (4,096 words) program (8,192 words) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 $0000 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f 0 1 jmpl instruction (jump to reset, stopc routine) jmpl instruction (jump to int routine) jmpl instruction (jump to timer a routine) jmpl instruction (jump to timer b, int routine) jmpl instruction (jump to timer c, int routine) jmpl instruction (jump to timer d, int routine) jmpl instruction (jump to int routine) jmpl instruction (jump to serial 1, serial 2 routine) 2 3 program (16,384 words) for HD404638R, hd40a4638r for hd404639r, hd40a4639r, hd407a4639r 4 8191 8192 $1fff $2000 figure 1 rom memory map vector address area ($0000?000f): reserved for jmpl instructions that branch to the start addresses of the reset and interrupt routines. after mcu reset or an interrupt, program execution continues from the vector address. zero-page subroutine area ($0000?003f): reserved for subroutines. the program branches to a subroutine in this area in response to the cal instruction. pattern area ($0000?0fff): contains rom data that can be referenced with the p instruction. program area ($0000?1fff (HD404638R, hd40a4638r), $0000?3fff (hd404639r, hd40a4639r, hd407a4639r)): used for program coding.
hd404639r series 7 ram memory map the mcu contains a 1,152-digit 4-bit ram area consisting of a memory register area, a data area, and a stack area. in addition, an interrupt control bits area, special register area, and register flag area are mapped onto the same ram memory space as a ram-mapped register area outside the above areas. the ram memory map is shown in figure 2 and described as follows. ram-mapped register area ($000?03f): interrupt control bits area ($000?003) this area is used for interrupt control bits (figure 3). these bits can be accessed only by ram bit manipulation instructions (sem/semd, rem/remd, and tm/tmd). however, note that not all the instructions can be used for each bit. limitations on using the instructions are shown in figure 4. special function register area ($004?01e, $024?03f) this area is used as mode registers and data registers for external interrupts, serial interface 1, serial interface 2, timer/counters, voltage comparator, and as data control registers for i/o ports. the structure is shown in figures 2 and 5. these registers can be classified into three types: write-only (w), read-only (r), and read/write (r/w). ram bit manipulation instructions cannot be used for these registers. register flag area ($020?023) this area is used for the dton, wdon, and other register flags and interrupt control bits (figure 3). these bits can be accessed only by ram bit manipulation instructions (sem/semd, rem/remd, and tm/tmd). however, note that not all the instructions can be used for each bit. limitations on using the instructions are shown in figure 4. memory register (mr) area ($040?04f): consisting of 16 addresses, this area (mr0?r15) can be accessed by register-register instructions (lamr and xmra). the structure is shown in figure 6. data area ($090?2ef): consists of 464 digits from $090 to $25f in two banks, which can be selected by setting the bank register (v: $03f). before accessing this area, set the bank register to the required value (figure 7). the area from $260 to $2ef is accessed without setting the bank register. stack area ($3c0?3ff): used for saving the contents of the program counter (pc), status flag (st), and carry flag (ca) at subroutine call (cal or call instruction) and for interrupts. this area can be used as a 16-level nesting subroutine stack in which one level requires four digits. the data to be saved and the save conditions are shown in figure 6. the program counter is restored by either the rtn or rtni instruction, but the status and carry flags can only be restored by the rtni instruction. any unused space in this area is used for data storage.
hd404639r series 8 compare control register data (464 digits) v = 1 (bank = 1) 0 $000 $000 64 80 608 960 1023 $040 $050 4 5 6 7 0 3 12 13 14 15 8 9 10 11 16 17 32 35 18 19 20 63 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $020 $023 $032 $033 $034 $035 $036 $037 $038 $03f $00a $00b $00e $00f w w r/w w w w w w w w w w w w w w w r r r r w r/w r/w r/w r/w r/w r/w $090 $25f 58 54 55 $3c0 $260 ram-mapped registers memory registers (mr) not used data (464 digits 2) v = 0 (bank 0) v = 1 (bank 1) data (144 digits) stack (64 digits) interrupt control bits area port mode register a serial mode register 1a serial data register 1 lower serial data register 1 upper timer mode register a timer mode register b1 timer b miscellaneous register timer mode register c1 timer c timer mode register b2 timer mode register d2 register flag area port r0 dcr port r1 dcr port r2 dcr port r3 dcr port d to d dcr port d to d dcr port d to d dcr not used v register 0 3 47 811 data (464 digits) v = 0 (bank = 0) the data area has two banks: bank 0 (v = 0) to bank 1 (v = 1) 10 11 14 15 timer read register b lower timer read register b upper timer read register c lower timer read register c upper timer write register b lower timer write register b upper timer write register c lower timer write register c upper r: w: r/w: $090 read only write only read/write note: * $011 $012 w w r r 17 18 timer read register d lower timer read register d upper timer write register d lower timer write register d upper 144 w timer mode register d1 r/w r/w timer d timer mode register c2 21 $015 22 $016 r compare data register 23 $017 36 $024 37 $025 38 $026 39 $027 40 $028 41 $029 42 $02a 43 $02b 24 25 27 26 28 29 30 31 $018 $019 $01a $01b $01c $01d $01e $01f $3ff compare enable register serial mode register 2a serial mode register 2b serial data register 2 lower serial data register 2 upper w w w w w w 60 44 45 46 47 port mode register b port mode register c detection edge select register 1 detection edge select register 2 serial mode register 1b system clock select register 1 not used not used port r4 dcr port r5 dcr port r6 dcr port r7 dcr w w w w w w w w w w w w w $02c $02d $02e $02f $031 $030 53 48 49 50 51 52 two registers are mapped on the same area. not used 752 $2f0 * r/w r/w r/w (pmra) (sm1a) (sr1l) (sr1u) (tma) (tmb1) (trbl/twbl) (trbu/twbu) (mis) (tmc1) (trcl/twcl) (trcu/twcu) (tmd1) (trdl/twdl) (trdu/twdu) (tmb2) (tmc2) (tmd2) (ccr) (cdr) (cer) (tgm) (tgc) (sm2a) (sm2b) (sr2l) (sr2u) (pmrb) (pmrc) (sm1b) (ssr1) (ssr2) (esr1) (esr2) (dcd0) (dcd1) (dcd2) (dcr0) (dcr1) (dcr2) (dcr3) (dcr4) (dcr5) (dcr6) (dcr7) (dcr8) (dcr9) (dcra) (dcrb) (dcrc) r/w r/w not used port r8 dcr port r9 dcr port ra dcr port rb dcr port rc dcr 59 57 56 $039 $03a $03b $03c (trbl) (trbu) (trcl) (trcu) (trdl) (trdu) (twbl) (twbu) (twcl) (twcu) (twdl) (twdu) tg mode register tg control register system clock select register 2 w w w figure 2 ram memory map
hd404639r series 9 0 1 2 3 bit 3 bit 2 bit 1 bit 0 imta (im of timer a) ifta (if of timer a) im1 (im of int 1 ) if1 (if of int 1 ) imtc (im of timer c) iftc (if of timer c) imtb (im of timer b) iftb (if of timer b) ims1 (im of serial interface 1) ifs1 (if of serial interface 1) imtd (im of timer d) iftd (if of timer d) $000 $001 $002 $003 interrupt control bits area im0 (im of int 0 ) if0 (if of int 0 ) rsp (reset sp bit) ie (interrupt enable flag) 32 33 34 35 icsf (input capture status flag) im3 (im of int 3 ) if3 (if of int 3 ) im2 (im of int 2 ) if2 (if of int 2 ) ims2 (im of serial interface 2) ifs2 (if of serial interface 2) im4 (im of int ) if4 (if of int ) $020 $021 $022 $023 register flag area dton (direct transfer on flag) wdon (watchdog on flag) lson (low speed on flag) icef (input capture error flag) rame (ram enable flag) not used if: im: ie: sp: interrupt request flag interrupt mask interrupt enable flag stack pointer bit 3 bit 2 bit 1 bit 0 4 4 not used figure 3 configuration of interrupt control bits and register flag areas ie im lson if icsf icef rame rsp wdon not used dton sem/semd rem/remd tm/tmd allowed allowed allowed not executed allowed allowed not executed allowed inhibited allowed not executed inhibited not executed in active mode allowed allowed used in subactive mode not executed not executed inhibited note: wdon is reset by mcu reset or by stopc enable for stop mode cancellation. dton is always reset in active mode. if the tm or tmd instruction is executed for the inhibited bits or non-existing bits, the value in st becomes invalid. figure 4 usage limitations of ram bit manipulation instructions
hd404639r series 10 $000 $003 pmra $004 sm1a $005 sr1l $006 sr1u $007 tma $008 tmb1 $009 trbl/twbl $00a trbu/twbu $00b mis $00c tmc1 $00d trcl/twcl $00e trcu/twcu $00f tmd1 $010 trdl/twdl $011 trdu/twdu $012 tmb2 $013 tmc2 $014 tmd2 $015 ccr $016 cdr $017 cer $018 tgm $019 tgc $01a sm2a $01b sm2b $01c sr2l $01d sr2u $01e $020 $023 pmrb $024 pmrc $025 esr1 $026 esr2 $027 sm1b $028 ssr1 $029 ssr2 $02a dcd0 $02c dcd1 $02d dcd2 $02e dcr0 $030 dcr1 $031 dcr2 $032 dcr3 $033 dcr4 $034 dcr5 $035 dcr6 $036 dcr7 $037 dcr8 $038 dcr9 $039 dcra $03a dcrb $03b dcrc $03c v $03f bit 3 bit 2 bit 1 interrupt control bits area r5 2 /si 2 r5 3 /so 2 r4 2 /si 1 r4 3 /so 1 serial transmit clock speed selection 1 serial data register 1 (lower digit) serial data register 1 (upper digit) clock source selection (timer a) clock source selection (timer b) timer b register (lower digit) timer b register (upper digit) so 1 pmos control interrupt frame period selection clock source selection (timer c) timer c register (lower digit) timer c register (upper digit) clock source selection (timer d) timer d register (lower digit) timer d register (upper digit) not used not used timer-b output mode selection not used timer-c output mode selection timer-d output mode selection internal reference voltages level result of each analog input comparison r5 1 / sck 2 serial transmit clock speed selection 2 register flag area r0 1 /int 2 r4 0 /evnd int 2 detection edge selection int 3 detection edge selection evnd detection edge selection not used not used not used port d 3 dcr port d 7 dcr port d 11 dcr port d 2 dcr port d 6 dcr port d 10 dcr port d 1 dcr port d 5 dcr port d 9 dcr port d 0 dcr port d 4 dcr port d 8 dcr not used port r0 3 dcr port r1 3 dcr port r2 3 dcr port r3 3 dcr port r4 3 dcr port r5 3 dcr port r6 3 dcr port r7 3 dcr port r0 2 dcr port r1 2 dcr port r2 2 dcr port r3 2 dcr port r4 2 dcr port r5 2 dcr port r6 2 dcr port r7 2 dcr port r0 1 dcr port r1 1 dcr port r2 1 dcr port r3 1 dcr port r4 1 dcr port r5 1 dcr port r6 1 dcr port r7 1 dcr port r0 0 dcr port r1 0 dcr port r2 0 dcr port r3 0 dcr port r4 0 dcr port r5 0 dcr port r6 0 dcr port r7 0 dcr not used not used not used 5. comparator switch 6. reference voltage selection 7. comparator selection 8. tonec output control 9. toner output control 2 10. so output control in idle states 11. serial clock source selection 2 12. so output level control in idle states 13. transmit clock source selection 1 1 r0 2 /int 3 d 12 / stopc d 13 / int 0 r0 0 / int 1 r3 3 / evnb r4 1 / sck 1 bit 0 not used so 2 pmos control serial data register 2 (lower digit) serial data register 2 (upper digit) not used system clock selection port r8 3 dcr port r9 3 dcr port ra 3 dcr port rb 3 dcr port r8 2 dcr port r9 2 dcr port ra 2 dcr port rb 2 dcr port r8 1 dcr port r9 1 dcr port ra 1 dcr port rb 1 dcr port r8 0 dcr port r9 0 dcr port ra 0 dcr port rb 0 dcr port rc 0 dcr tonec output frequency toner output frequency dtmf enable not used system clock selection system clock division rate not used not used not used 1. timer-a/time-base 2. auto-reload on/off 3. pull-up mos control 4. input capture selection notes: 14. 32-khz oscillation stop 15. 32-khz oscillation division ratio 16. bank 0 to bank 1 selection r0 3 /int 4 int 4 detection edge selection not used * 2 * 3 * 4 * 2 * 2 * 5 * 8 * 6 * 9 * 7 * 10 * 11 * 14 * 15 * 12 * 13 * 16 * 1 figure 5 special function register area
hd404639r series 11 memory registers 64 65 66 67 68 69 70 71 73 74 75 76 77 78 79 72 $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04a $04b $04c $04d $04e $04f 960 $3c0 1023 $3ff mr(0) mr(1) mr(2) mr(3) mr(4) mr(5) mr(6) mr(7) mr(8) mr(9) level 16 level 15 level 14 level 13 level 12 level 11 level 10 level 9 level 8 level 7 level 6 level 5 level 4 level 3 level 2 level 1 mr(10) mr(11) mr(12) mr(13) mr(14) mr(15) pc pc pc pc pc pc pc pc pc pc pc pc st pc ca pc 10 3 13 9 6 2 12 8 5 1 11 7 4 0 bit 3 bit 2 bit 1 bit 0 $3fc $3fd $3fe $3ff 1020 1021 1022 1023 pc ?c : st: status flag ca: carry flag program counter 13 stack area 0 figure 6 configuration of memory registers and stack area, and stack position bit initial value read/write bit name 3 not used 2 not used 0 0 r/w v0 1 not used v0 0 1 bank area selection bank 0 is selected bank 1 is selected note: after reset, the value in the bank register is 0, and therefore bank 0 is selected. bank register (v: $03f) figure 7 bank register (v)
hd404639r series 12 functional description registers and flags the mcu has nine registers and two flags for cpu operations. they are shown in figure 8 and described below. 30 30 30 30 30 30 0 0 0 13 95 1 (b) (a) (w) (x) (y) (spx) (spy) (ca) (st) (pc) (sp) 1111 accumulator b register w register x register y register spx register spy register carry status program counter initial value: 0, no r/w stack pointer initial value: $3ff, no r/w 0 0 initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: 1, no r/w figure 8 registers and flags accumulator (a), b register (b): four-bit registers used to hold the results from the arithmetic logic unit (alu) and transfer data between memory, i/o, and other registers. w register (w), x register (x), y register (y): two-bit (w) and four-bit (x and y) registers used for indirect ram addressing. the y register is also used for d-port addressing.
hd404639r series 13 spx register (spx), spy register (spy): four-bit registers used to supplement the x and y registers. carry flag (ca): one-bit flag that stores any alu overflow generated by an arithmetic operation. ca is affected by the sec, rec, rotl, and rotr instructions. a carry is pushed onto the stack during an interrupt and popped from the stack by the rtni instruction?ut not by the rtn instruction. status flag (st): one-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the alu, or result of a bit test. st is used as a branch condition of the br, brl, cal, and call instructions. the contents of st remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the br, brl, cal, or call instruction is read, regardless of whether the instruction is executed or skipped. the contents of st are pushed onto the stack during an interrupt and popped from the stack by the rtni instruction?ut not by the rtn instruction. program counter (pc): 14-bit binary counter that points to the rom address of the instruction being executed. stack pointer (sp): ten-bit pointer that contains the address of the stack area to be used next. the sp is initialized to $3ff by mcu reset. it is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. the top four bits of the sp are fixed at 1111, so a stack can be used up to 16 levels. the sp can be initialized to $3ff in another way: by resetting the rsp bit with the rem or remd instruction. reset the mcu is reset by inputting a high-level voltage to the reset pin. at power-on or when stop mode is cancelled, reset must be high for at least one t rc to enable the oscillator to stabilize. during operation, reset must be high for at least two instruction cycles. initial values after mcu reset are listed in table 1.
hd404639r series 14 table 1 initial values after mcu reset item abbr. initial value contents program counter (pc) $0000 indicates program execution point from start address of rom area status flag (st) 1 enables conditional branching stack pointer (sp) $3ff stack level 0 interrupt flags/mask interrupt enable flag (ie) 0 inhibits all interrupts interrupt request flag (if) 0 indicates there is no interrupt request interrupt mask (im) 1 prevents (masks) interrupt requests i/o port data register (pdr) all bits 1 enables output at level 1 data control register (dcd0?cd2) all bits 0 turns output buffer off (to high impedance) (dcr0?crc) all bits 0 port mode register a (pmra) 0000 refer to description of port mode register a port mode register b (pmrb) 0000 refer to description of port mode register b port mode register c bits 3, 1, 0 (pmrc3, pmrc1, pmrc0) 000 refer to description of port mode register c detection edge select register 1 (esr1) 0000 disables edge detection detection edge select register 2 (esr2) 0000 disables edge detection timer/ counters, timer mode register a (tma) 0000 refer to description of timer mode register a serial interface timer mode register b1 (tmb1) 0000 refer to description of timer mode register b1 timer mode register b2 (tmb2) - - 00 refer to description of timer mode register b2 timer mode register c1 (tmc1) 0000 refer to description of timer mode register c1 timer mode register c2 (tmc2) - 000 refer to description of timer mode register c2 timer mode register d1 (tmd1) 0000 refer to description of timer mode register d1 timer mode register d2 (tmd2) 0000 refer to description of timer mode register d2 notes: 1. the statuses of other registers and flags after mcu reset are shown in the following table. 2. x indicates invalid value. ?indicates that the bit does not exist.
hd404639r series 15 item abbr. initial value contents timer/ counters, serial mode register 1a (sm1a) 0000 refer to description of serial mode register 1a serial interface serial mode register 1b (sm1b) - - x0 refer to description of serial mode register 1b serial mode register 2a (sm2a) 0000 refer to description of serial mode register 2a serial mode register 2b (sm2b) - 0x0 refer to description of serial mode register 2b prescaler s (pss) $000 prescaler w (psw) $00 timer counter a (tca) $00 timer counter b (tcb) $00 timer counter c (tcc) $00 timer counter d (tcd) $00 timer write register b (twbu, twbl) $x0 timer write register c (twcu, twcl) $x0 timer write register d (twdu, twdl) $x0 octal counter 000 comparator compare control register (ccr) 0000 refer to description of voltage comparator compare enable register (cer) 0000 refer to description of voltage comparator bit register low speed on flag (lson) 0 refer to description of operating modes watchdog timer on flag (wdon) 0 refer to description of timer c direct transfer on flag (dton) 0 refer to description of operating modes input capture status flag (icsf) 0 refer to description of timer d input capture error flag (icef) 0 refer to description of timer d others miscellaneous register (mis) 0000 refer to description of operating modes, and oscillator circuit system clock select register 1 bits 2? (ssr12 ssr10) 000 refer to description of operating modes, and oscillator circuit system clock select register 2 (ssr2) 0000 bank register (v) - - - 0 refer to description of ram memory map notes: 1. the statuses of other registers and flags after mcu reset are shown in the following table. 2. x indicates invalid value. ?indicates that the bit does not exist.
hd404639r series 16 item abbr. status after cancellation of stop mode by stopc input status after cancellation of stop mode by mcu reset status after all other types of reset carry flag (ca) pre-stop-mode values are not guaranteed; values must be initialized by program pre-stop-mode values are not guaranteed; values must be initialized by program accumulator (a) b register (b) w register (w) x/spx register (x/spx) y/spy register (y/spy) serial data register (srl, sru) ram pre-stop-mode values are retained ram enable flag (rame) 1 0 0 port mode register c bit 2 (pmrc2) pre-stop-mode values are retained 00 system clock select register 1 bit 3 (ssr13) interrupts the mcu has 11 interrupt sources: five external signals ( i nt 0 , i nt 1 , int 2 , int 3 , int 4 ), four timer/counters (timers a, b, c, and d), and two serial interfaces (serial interface 1, serial interface 2). an interrupt request flag (if), interrupt mask (im), and vector address are provided for each interrupt source, and an interrupt enable flag (ie) controls the entire interrupt process. some vector addresses are shared by two different interrupts. they are timer b and int 2 , timer c and int 3 , timer d and int 4 , and serial interface 1 and serial interface 2. so the type of request that has occurred must be checked at the beginning of interrupt processing. interrupt control bits and interrupt processing: locations $000 to $003 and $022 to $023 in ram are reserved for the interrupt control bits which can be accessed by ram bit manipulation instructions. the interrupt request flag (if) cannot be set by software. mcu reset initializes the interrupt enable flag (ie) and the if to 0 and the interrupt mask (im) to 1. a block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 11 interrupt sources are listed in table 3.
hd404639r series 17 an interrupt request occurs when the if is set to 1 and the im is set to 0. if the ie is 1 at that point, the interrupt is processed. a priority programmable logic array (pla) generates the vector address assigned to that interrupt source. the interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in figure 11. after an interrupt is acknowledged, the previous instruction is completed in the first cycle. the ie is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. program the jmpl instruction at each vector address to branch the program to the start address of the interrupt program, and reset the if by a software instruction within the interrupt program. table 2 vector addresses and interrupt priorities reset/interrupt priority vector address reset, stopc * $0000 int 0 1 $0002 int 1 2 $0004 timer a 3 $0006 timer b, int 2 4 $0008 timer c, int 3 5 $000a timer d, int 4 6 $000c serial 1 and 2 7 $000e note: * the stopc interrupt request is valid only in stop mode table 3 interrupt processing and activation conditions interrupt source interrupt control bit int 0 int 1 timer a timer b or int 2 timer c or int 3 timer d or int 4 serial 1 or serial 2 ie 111 1 1 1 1 if0 . im0 100 0 0 0 0 if1 . im1 * 100000 ifta . imta ** 10000 iftb . imtb + if2 . im2 *** 1000 iftc . imtc + if3 . im3 *** * 100 iftd . imtd + if4 . im4 *** * * 10 ifs1 . ims1 + ifs2 . ims2 *** * * * 1 note: * can be either 0 or 1. their values have no effect on operation.
hd404639r series 18 ie ifo imo if1 im1 ifta imta iftb imtb iftc imtc iftd imtd $ 000,0 $ 000,2 $ 000,3 $ 001,0 $ 001,1 $ 001,2 $ 001,3 $ 002,0 $ 002,1 $ 002,2 $ 002,3 $ 003,0 $ 003,1 sequence control ?push pc/ca/st ?reset ie ?jump to vector address priority control logic vector address note: $m,n is ram address $m, bit number n. $ 003,2 $ 003,3 int 0 interrupt int 1 interrupt timer a interrupt timer b interrupt timer c interrupt timer d interrupt serial 1 interrupt if2 im2 if3 im3 if4 im4 $ 022,0 $ 022,1 $ 022,2 $ 022,3 $ 023,0 $ 023,1 ifs2 ims2 $ 023,2 $ 023,3 int 2 interrupt int 3 interrupt int interrupt serial 2 interrupt ifs1 ims1 4 figure 9 interrupt control circuit
hd404639r series 19 instruction cycles 123456 instruction execution ie reset interrupt acceptance execution of jmpl instruction at vector address execution of instruction at start address of interrupt routine vector address generation note: the stack is accessed and the ie reset after the instruction is executed, even if it is a two-cycle instruction. * stacking * figure 10 interrupt processing sequence
hd404639r series 20 power on reset = 1? reset mcu interrupt request? execute instruction pc (pc) + 1 ? pc $0002 ? pc $0004 ? pc $0006 ? pc $0008 ? pc $000a ? pc $000e ? ie = 1? accept interrupt ie 0 stack (pc) stack (ca) stack (st) ? int 0 interrupt? int 1 interrupt? timer-a interrupt? timer-b/int 2 interrupt? no yes no yes no yes yes yes yes yes yes no no no no ? ? ? (serial 1, serial 2 interrupt) pc $000c ? timer-d/int interrupt? yes no no timer-c/int 3 interrupt? 4 figure 11 interrupt processing flowchart
hd404639r series 21 interrupt enable flag (ie: $000, bit 0): controls the entire interrupt process. it is reset by the interrupt processing and set by the rtni instruction, as listed in table 4. table 4 interrupt enable flag (ie: $000, bit 0) ie interrupt enabled/disabled 0 disabled 1 enabled external interrupts ( int 0 , int 1 , int 2 ?nt 4 ): five external interrupt signals. external interrupt request flags (if0?f4: $000, $001, $022, $023): if0 and if1 are set at the falling edge of signals input to int 0 and int 1 , and if2?f4 are set at the rising or falling edge of signals input to int 2 ?nt 4 , as listed in table 5. the int 2 ?nt 4 interrupt edges are selected by the detection edge select registers (esr1, esr2: $026, $027) as shown in figures 12 and 13. table 5 external interrupt request flags (if0?f4: $000, $001, $022, $023) if0?f4 interrupt request 0no 1 yes bit initial value read/write bit name 3 0 w esr13 2 0 w esr12 0 0 w esr10 1 0 w esr11 detection edge selection register 1 (esr1: $026) esr11 0 1 esr10 0 1 0 1 int 2 detection edge no detection falling-edge detection rising-edge detection double-edge detection esr13 0 1 esr12 0 1 0 1 int 3 detection edge no detection falling-edge detection rising-edge detection double-edge detection note: both falling and rising edges are detected. * * * figure 12 detection edge selection register 1 (esr1)
hd404639r series 22 bit initial value read/write bit name 3 0 w esr23 2 0 w esr22 0 0 w 1 0 w esr21 detection edge selection register 2 (esr2: $027) esr23 0 1 esr22 0 1 0 1 evnd detection edge no detection falling-edge detection rising-edge detection double-edge detection note: both falling and rising edges are detected. esr20 * esr21 0 1 esr20 0 1 0 1 int detection edge no detection falling-edge detection rising-edge detection double-edge detection 4 * * figure 13 detection edge selection register 2 (esr2) external interrupt masks (im0?m4: $000, $001, $022, $023): prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. table 6 external interrupt masks (im0?m4: $000, $001, $022, $023) im0?m4 interrupt request 0 enabled 1 disabled (masked) timer a interrupt request flag (ifta: $001, bit 2): set by overflow output from timer a, as listed in table 7. table 7 timer a interrupt request flag (ifta: $001, bit 2) ifta interrupt request 0no 1 yes timer a interrupt mask (imta: $001, bit 3): prevents (masks) an interrupt request caused by the timer a interrupt request flag, as listed in table 8.
hd404639r series 23 table 8 timer a interrupt mask (imta: $001, bit 3) imta interrupt request 0 enabled 1 disabled (masked) timer b interrupt request flag (iftb: $002, bit 0): set by overflow output from timer b, as listed in table 9. table 9 timer b interrupt request flag (iftb: $002, bit 0) iftb interrupt request 0no 1 yes timer b interrupt mask (imtb: $002, bit 1): prevents (masks) an interrupt request caused by the timer b interrupt request flag, as listed in table 10. table 10 timer b interrupt mask (imtb: $002, bit 1) imtb interrupt request 0 enabled 1 disabled (masked) timer c interrupt request flag (iftc: $002, bit 2): set by overflow output from timer c, as listed in table 11. table 11 timer c interrupt request flag (iftc: $002, bit 2) iftc interrupt request 0no 1 yes timer c interrupt mask (imtc: $002, bit 3): prevents (masks) an interrupt request caused by the timer c interrupt request flag, as listed in table 12. table 12 timer c interrupt mask (imtc: $002, bit 3) imtc interrupt request 0 enabled 1 disabled (masked)
hd404639r series 24 timer d interrupt request flag (iftd: $003, bit 0): set by overflow output from timer d, or by the rising or falling edge of signals input to evnd when the input capture function is used, as listed in table 13. table 13 timer d interrupt request flag (iftd: $003, bit 0) iftd interrupt request 0no 1 yes timer d interrupt mask (imtd: $003, bit 1): prevents (masks) an interrupt request caused by the timer d interrupt request flag, as listed in table 14. table 14 timer d interrupt mask (imtd: $003, bit 1) imtd interrupt request 0 enabled 1 disabled (masked) serial interrupt request flags (ifs1: $003, bit 2; ifs2: $023, bit 2): set when data transfer is completed or when data transfer is suspended, as listed in table 15. table 15 serial interrupt request flag (ifs1: $003, bit 2; ifs2: $023, bit 2) ifs1, ifs2 interrupt request 0no 1 yes serial interrupt masks (ims1: $003, bit 3; ims2: $023, bit 3): prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 16. table 16 serial interrupt mask (ims1: $003, bit 3; ims2: $023, bit 3) ims1, ims2 interrupt request 0 enabled 1 disabled (masked)
hd404639r series 25 operating modes the mcu has five operating modes as shown in table 17. the operations in each mode are listed in tables 18 and 19. transitions between operating modes are shown in figure 14. table 17 operating modes and clock status mode name active standby stop watch subactive activation method reset cancellation, interrupt request stopc cancellation in stop mode, stop/sby instruction in subactive mode (when direct transfer is selected) sby instruction stop instruction when tma3 = 0 stop instruction when tma3 = 1 stop/sby instruction in subactive mode (when direct transfer is not selected) int 0 or timer a interrupt request from watch mode when lson = 1 status system oscillator op op stopped stopped stopped subsystem oscillator op op op * 1 op op cancellation method reset input, stop/sby instruction reset input, interrupt request reset input, stopc input in stop mode reset input, int 0 or timer a interrupt request reset input, stop/sby instruction notes: op implies in operation 1. operating or stopping the oscillator can be selected by setting bit 3 of system clock select register 1 (ssr1: $029).
hd404639r series 26 table 18 operations in low-power dissipation modes function stop mode watch mode standby mode subactive mode cpu reset retained retained op ram retained retained retained op timer a reset op op op timer b reset stopped op op timer c reset stopped op op timer d reset stopped op op serial interface 1, 2 reset stopped * 2 op op dtmf reset reset op reset comparator reset stopped stopped op i/o reset * 1 retained retained op notes: op implies in operation 1. output pins are at high impedance. 2. transmission/reception is activated if a clock is input in external clock mode. however, all interrupts stop. table 19 i/o status in low-power dissipation modes output input standby mode, watch mode stop mode active mode, subactive mode d 0 ? 11 retained high impedance input enabled d 12 ? 13 , rd 0 ?d 3 , re 0 input enabled r0 0 ?c 1 retained or output of peripheral functions high impedance input enabled
hd404639r series 27 reset by reset input or by watchdog timer f osc : f x : cpu : clk : per : oscillate oscillate stop f cyc f cyc f osc : f x : cpu : clk : per : oscillate oscillate stop f w f cyc f osc : f x : cpu : clk : per : oscillate oscillate f cyc f cyc f cyc f osc : f x : cpu : clk : per : oscillate oscillate f cyc f w f cyc f osc : f x : cpu : clk : per : stop oscillate f sub f w f sub f osc : f x : cpu : clk : per : stop stop stop stop stop f osc : f x : cpu : clk : per : stop oscillate stop f w stop f osc : f x : cpu : clk : per : stop oscillate stop f w stop standby mode stop mode (tma3 = 0, ssr13 = 1) watch mode subactive mode (tma3 = 1) (tma3 = 1, lson = 0) (tma3 = 1, lson = 1) sby interrupt sby interrupt stop int 0 , timer a stop 2 1. interrupt source 2. stop/sby (dton = 1, lson = 0) 3. stop/sby (dton = 0, lson = 0) 4. stop/sby (dton = don? care, lson = 1) f osc : f x : f cyc : f sub : f w : lson: dton: main oscillation frequency suboscillation frequency for time-base f /4 or f /8 or f /16 or f /32 (software selectable) osc f x /8 or f x /4 (software selectable) f x /8 system clock clock for time-base clock for other peripheral functions low speed on flag direct transfer on flag active mode notes: cpu : clk : per : f osc : f x : cpu : clk : per : stop oscillate stop stop stop (tma3 = 0, ssr13 = 0) reset1 reset2 rame = 0 rame = 1 int 0 , timer a (tma3 = 0) stop stopc stopc stop osc osc osc * 3 * 4 * 1 * 1 * figure 14 mcu status transitions
hd404639r series 28 active mode: all mcu functions operate according to the clock generated by the system oscillators osc 1 and osc 2 . standby mode: in standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. therefore, the cpu operation stops, but all ram and register contents are retained, and the d or r port status, when set to output, is maintained. peripheral functions such as interrupts, timers, and serial interface continue to operate. the power dissipation in this mode is lower than in active mode because the cpu stops. the mcu enters standby mode when the sby instruction is executed in active mode. standby mode is terminated by a reset input or an interrupt request. if it is terminated by reset input, the mcu is reset as well. after an interrupt request, the mcu enters active mode and executes the next instruction after the sby instruction. if the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. a flowchart of operation in standby mode is shown in figure 15. stop mode: in stop mode, all mcu operations stop and ram data is retained. therefore, the power dissipation in this mode is the least of all modes. the osc 1 and osc 2 oscillator stops. for the x1 and x2 oscillator to operate or stop can be selected by setting bit 3 of system clock select register 1 (ssr1: $029; operating: ssr13 = 0, stop: ssr13 = 1) (figure 24). the mcu enters stop mode if the stop instruction is executed in active mode when bit 3 of timer mode register a (tma: $008) is set to 0 (tma3 = 0) (figure 41). stop mode is terminated by a reset input or a stopc input as shown in figure 16. reset or stopc must be applied for at least one t rc to stabilize oscillation (refer to the ac characteristics section). when the mcu restarts after stop mode is cancelled, all ram contents before entering stop mode are retained, but the accuracy of the contents of the accumulator, b register, w register, x/spx register, y/spy register, carry flag, and serial data register cannot be guaranteed. watch mode: in watch mode, the clock function (timer a) using the x1 and x2 oscillator operates but other function operations stop. therefore, the power dissipation in this mode is the second least to stop mode, and this mode is convenient when only clock display is used. in this mode, the osc 1 and osc 2 oscillator stops, but the x1 and x2 oscillator operates. the mcu enters watch mode if the stop instruction is executed in active mode when tma3 = 1, or if the stop or sby instruction is executed in subactive mode. watch mode is terminated by a reset input or a timer-a/ int 0 interrupt request. for details of reset input, refer to the stop mode section. when terminated by a timer-a/ int 0 interrupt request, the mcu enters active mode if lson is 0, or subactive mode if lson is 1. after an interrupt request is generated, the time required to enter active mode is t rc for a timer a interrupt, and t x (where t + t rc < t x < 2t + t rc ) for an int 0 interrupt, as shown in figures 17 and 18. operation during mode transition is the same as that at standby mode cancellation (figure 15).
hd404639r series 29 standby oscillator: active peripheral clocks: active all other clocks: stop no yes no yes no yes no yes no yes no yes yes (sby only) watch oscillator: stop suboscillator: active peripheral clocks: stop all other clocks: stop restart processor clocks reset mcu execute next instruction accept interrupt restart processor clocks no yes if = 1, im = 0, and ie = 1? reset = 1? if0 ? im0 = 1? if1 ? im1 = 1? ifta ? imta = 1? iftb ? imtb + if2 ? im2 = 1? iftc ? imtc + if3 ? im3 = 1? iftd imtd + if4 im4 = 1? no yes ifs1 ? ims1 + ifs2 ? ims2 = 1? no stop oscillator: stop suboscillator: active/stop peripheral clocks: stop all other clocks: stop reset = 1? stopc = 0? rame = 1 rame = 0 yes yes no no execute next instruction (sby only) (sby only) (sby only) (sby only) figure 15 mcu operation flowchart
hd404639r series 30

stop mode oscillator internal clock stop instruction execution t res 3 t rc (stabilization period) t res reset stopc figure 16 timing of stop mode cancellation subactive mode: the osc 1 and osc 2 oscillator stops and the mcu operates with a clock generated by the x1 and x2 oscillator. in this mode, functions other than the dtmf generator operate. however, because the operating clock is slow, the power dissipation becomes low, next to watch mode. the cpu instruction execution speed can be selected as 244 m s or 122 m s by setting bit 2 (ssr12) of system clock select register 1 (ssr1: $029). note that the ssr12 value must be changed in active mode. if the value is changed in subactive mode, the mcu may malfunction. when the stop or sby instruction is executed in subactive mode, the mcu enters either watch or active mode, depending on the statuses of the low speed on flag (lson: $020, bit 0) and the direct transfer on flag (dton: $020, bit 3). subactive mode is an optional function that the user must specify on the function option list. interrupt frame: in watch and subactive modes, f clk is applied to timer a and the int 0 circuit. prescaler w and timer a operate as the time-base and generate the timing clock for the interrupt frame. three interrupt frame lengths (t) can be selected by setting the miscellaneous register (mis: $00c) (figure 18). in watch and subactive modes, the timer-a/ int 0 interrupt is generated synchronously with the interrupt frame. the interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. the falling edge of the int 0 signal is input asynchronously with the interrupt frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. an overflow and interrupt request in timer a is generated synchronously with t he interrupt strobe timing. note on use: when the mcu is in watch mode or sub-active mode and if the high level period before the falling edge of int 0 is shorter than the interrupt frame or if the low level period after the falling edge of int 0 is shorter than the interrupt frame, int 0 is not detected. therefore, the high or low level period of int 0 must be held longer than the interrupt frame when the mcu is in watch mode or subactive mode.
hd404639r series 31 t rc t t x t t: t : interrupt frame length oscillation stabilization period rc note : if the time from the fall of the int 0 signal until the interrupt is accepted and active mode is entered is t x , then t x will be in the following range : t + t rc t x 2t + t rc (during the transition from watch mode to active mode only) interrupt strobe int 0 interrupt request generation active mode watch mode active mode oscillation stabilization period figure 17 interrupt frame bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 miscellaneous register (mis: $00c) mis1 0 mis0 t 1 0 0.24414 ms t rc 0.12207 ms 0.24414 ms 7.8125 ms 31.25 ms oscillation circuit conditions external clock input ceramic oscillator 0 1 1 1 0 1 15.625 ms 62.5 ms not used notes: 1. 2. the values of t and t rc are applied when a 32.768-khz crystal oscillator is used. the value is applied only when direct transfer operation is used. buffer control. refer to figure 38. mis3 mis2 crystal oscillator * 1 * 2 * figure 18 miscellaneous register (mis)
hd404639r series 32 direct transition from subactive mode to active mode: available by controlling the direct transfer on flag (dton: $020, bit 3) and the low speed on flag (lson: $020, bit 0). the procedures are described below: set lson to 0 and dton to 1 in subactive mode. execute the stop or sby instruction. the mcu automatically enters active mode from subactive mode after waiting for the mcu internal processing time and oscillation stabilization time (figure 19). notes: 1. the dton flag ($020, bit 3) can be set only in subactive mode. it is always reset in active mode. 2. the transition time (t d ) from subactive mode to active mode: t rc < t d < t + t rc subactive mode interrupt strobe direct transfer completion timing mcu internal processing period oscillation stabilization time active mode t t rc t: t rc : t d : stop/sby instruction execution (set lson = 0, dton = 1) interrupt frame length oscillation stabilization period transition time t d figure 19 direct transition timing stop mode cancellation by stopc : the mcu enters active mode from stop mode by a stopc input as well as by reset. in either case, the mcu starts instruction execution from the starting address (address 0) of the program. however, the value of the ram enable flag (rame: $021, bit 3) differs between cancellation by stopc and by reset. when stop mode is cancelled by reset, rame = 0; when cancelled by stopc , rame = 1. reset can cancel all modes, but stopc is valid only in stop mode; stopc input is ignored in other modes. therefore, when the program requires to confirm that stop mode has been cancelled by stopc (for example, when the ram contents before entering stop mode are used after transition to active mode), execute the test instruction on the ram enable flag (rame) at the beginning of the program. mcu operation sequence: the mcu operates in the sequences shown in figures 20 to 22. it is reset by an asynchronous reset input, regardless of its status. the low-power mode operation sequence is shown in figure 22. with the ie flag cleared and an interrupt flag set together with its interrupt mask cleared, if a stop/sby instruction is executed, the instruction is
hd404639r series 33 cancelled (regarded as an nop) and the following instruction is executed. before executing a stop/sby instruction, make sure all interrupt flags are cleared or all interrupts are masked. power on reset = 1 ? rame = 0 reset mcu mcu operation cycle no yes figure 20 mcu operating sequence (power on)
hd404639r series 34 mcu operation cycle if = 1? instruction execution sby/stop instruction? pc next location pc vector address low-power mode operation cycle ie 0 stack (pc), (ca), (st) im = 0 and ie = 1? ? ? ? yes no no yes yes no if: im: ie: pc: ca: st: ? interrupt request flag interrupt mask interrupt enable flag program counter carry flag status flag figure 21 mcu operating sequence (mcu operation cycle)
hd404639r series 35 low-power mode operation cycle if = 1 and im = 0? hardware nop execution ? pc next iocation mcu operation cycle standby/watch mode if = 1 and im = 0? hardware nop execution pc next iocation ? instruction execution stop mode no yes no yes for if and im operation, refer to figure 15. stopc = 0? rame = 1 reset mcu no yes figure 22 mcu operating sequence (low-power mode operation)
hd404639r series 36 internal oscillator circuit a block diagram of the clock generation circuit is shown in figure 23. as shown in table 20, a ceramic oscillator or crystal oscillator can be connected to osc 1 and osc 2 , and a 32.768-khz oscillator can be connected to x1 and x2. the system oscillator can also be operated by an external clock. system clock select register 1 (ssr1: $029) and system clock select register 2 (ssr2: $02a) must be selected according to the frequency of the oscillator connected to osc 1 and osc 2 (figure 24). note: if the ssr10, ssr11, ssr22 and ssr23 setting does not match the oscillator frequency, the dtmf generator and subsystems using the 32.768-khz oscillation will malfunction. osc 2 osc 1 x1 x2 system oscillator sub- system oscillator 1/4 or 1/8 or 1/16 or 1/32 division circuit* timing generator circuit system clock selection cpu with rom, ram, registers, flags, and i/o peripheral function interrupt time-base interrupt time-base clock selection 1/8 or 1/4 division circuit* timing generator circuit timing generator circuit 1/8 division circuit f w f sub t subcyc lson tma3 f cyc t cyc f osc f x t wcyc cpu per clk notes: 1. 2. 1 2 1/4, 1/8, 1/16 or 1/32 division ratio can be selected by setting bits 1 and 0 of system clock select register 2 (ssr2: $02a). 1/8 or 1/4 division ratio can be selected by setting bit 2 of system clock select register 1 (ssr1: $029). figure 23 clock generation circuit
hd404639r series 37 bit initial value read/write bit name 3 0 w ssr13 2 0 w ssr12 0 0 w ssr10 1 0 w ssr11 system clock select register 1 (ssr1: $029) 400 khz 800 khz 2 mhz 4 mhz 3.58 mhz 8 mhz 7.16 mhz 0 1 don? care 1 don? care 0 1 ratio selection f sub = f x /8 f sub = f x /4 ssr13 0 1 32-khz oscillation stop oscillation operates in stop mode oscillation stops in stop mode 32-khz oscillation division ssr12 0 1 0 1 0 1 0 1 0 1 don? care 1 don? care system clock selection ssr23 ssr22 ssr11 ssr10 figure 24 system clock select register 1 (ssr1) gnd x2 x1 reset osc 2 osc 1 test gnd figure 25 typical layouts of crystal and ceramic oscillator
hd404639r series 38 the division ratio of the system clock can be selected as 1/4, 1/8, 1/16, or 1/32 by setting bits 0 and 1 (ssr20, ssr21) of system clock select register 2 (ssr2: $02a). the values of ssr20 and ssr21 are valid after the mcu enters watch mode (ssr22 and ssr23 are valid directly). the system clock must be stopped when the division ratio is to be changed. there are two ways for setting the division ratio of the system clock. the division ratio is selected by setting ssr20 and ssr21 in active mode (at this time, the presetting values of ssr20 and ssr21 are valid). this causes the mcu to enter watch mode (system clock is stopped). when the mcu enters active mode from watch mode, the setting values of ssr20 and ssr21 become valid. the division ratio can also be selected by setting ssr20 and ssr21 in subactive mode. this causes the mcu to enter active mode via watch mode, thus validating the setting values of ssr20 and ssr21 (so does the case of direct transition). after reset input or after stop mode has been cancelled, the division ratio of the system clock can be selected as 1/4 or 1/32 by setting the sel pin level. 1/4 division ratio: connect sel to v cc . 1/32 division ratio: connect sel to gnd. the division ratio of the subsystem clock can be selected as 1/4 or 1/8 by setting bit 2 (ssr12) of system clock select register 1 (ssr1: $029). ssr12 is valid directly after being set, but in order to change the value of ssr12, the mcu must be in active mode. if ssr12 is changed in subactive mode, the mcu will malfunction.
hd404639r series 39 bit initial value read/write bit name 3 0 w ssr23 2 0 w ssr22 0 0 w ssr20 1 0 w ssr21 system clock select register 2 (ssr2: $02a) ssr21 0 1 ssr20 0 1 0 1 system clock division ratio 1/4 division 1/8 division 1/16 division 1/32 division ssr22 0 1 system clock selection selected from 400 khz, 800 khz, 2 mhz, 4 mhz * 2 notes: 3.58 mhz 8 mhz * 2 7.16 mhz 1. the dtmf frequencies are not affected by the setting of the system clock division ratio. 2. refer to system clock select register 1 (ssr1) of figure 24. * 1 ssr23 0 0 1 1 figure 26 system clock select register 2 (ssr2)
hd404639r series 40 table 20 oscillator circuit examples circuit configuration circuit constants external clock operation external oscillator osc open 1 osc 2 ceramic oscillator (osc 1 , osc 2 ) osc 2 c 1 2 c osc 1 r f ceramic oscillator gnd ceramic oscillator: csb400p22 (murata), csb400p (murata) r f = 1 m w 20% c 1 = c 2 = 220 pf 5% ceramic oscillator: csb800j122 (murata), csb800j (murata) r f = 1 m w 20% c 1 = c 2 = 220 pf 5% ceramic oscillator: csa2.00mg (murata) r f = 1 m w 20% c 1 = c 2 = 30 pf 20% ceramic oscillator: csa4.00mg (murata) r f = 1 m w 20% c 1 = c 2 = 30 pf 20% ceramic oscillator: csa3.58mg (murata) r f = 1 m w 20% c 1 = c 2 = 30 pf 20% ceramic oscillator: csa8.00mt (murata) r f = 1 m w 20% c 1 = c 2 = 30 pf 20%
hd404639r series 41 circuit configuration circuit constants crystal oscillator (osc 1 , osc 2 ) c 1 2 c crystal oscillator gnd l s c r s c 0 f r osc 1 osc 2 osc 2 osc 1 r f = 1 m w 20% c 1 = c 2 = 10?2 pf 20% crystal: equivalent to circuit shown below c 0 = 7 pf max r s = 100 w max f = 400 khz, 800 khz, 2 mhz, 3.58 mhz, 4 mhz, 7.16 mhz, 8 mhz crystal oscillator (x1, x2) x1 c 1 2 c x2 crystal oscillator gnd l s c r s c 0 x1 x2 crystal: 32.768 khz: mx38t (nippon denpa) c 1 = c 2 = 20 pf 20% r s : 14 k w c 0 : 1.5 pf notes: 1. since the circuit constants change depending on the crystal or ceramic oscillator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. wiring among osc 1 , osc 2 , x1, x2, and elements should be as short as possible, and must not cross other wiring (see figure 25). 3. if the 32.768-khz crystal oscillator is not used, the x1 pin must be fixed to v cc and x2 must be open.
hd404639r series 42 input/output the mcu has 61 input/output pins (d 0 ? 11 , r0 0 ?c 0 ) and 7 input pins (d 12 , d 13, rd 0 ?d 3 , re 0 ). the features are described below. a maximum current of 15 ma is allowed for each of the pins d 4 to d 11 with a total maximum current of less than 105 ma. in addition, d 0 ? 3 can each act as a 10-ma maximum current source. some input/output pins are multiplexed with peripheral function pins such as those for the timers or serial interface. for these pins, the peripheral function setting is done prior to the d or r port setting. therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. peripheral function output pins are cmos output pins. only the r4 3 /so 1 and r5 3 /so 2 pins can be set to nmos open-drain output by software. in stop mode, the mcu is reset, and therefore peripheral function selection is cancelled. input/output pins are in high-impedance state. pins d 0 ? 3 have built-in pull-down mos, and other input/output pins have built-in pull-up mos, which can be individually turned on or off by software. i/o buffer configuration is shown in figure 27, programmable i/o circuits are listed in table 21, and i/o pin circuit types are shown in table 22. table 21-1 programmable i/o circuits (with pull-up mos) mis3 (bit 3 of mis) 0 1 dcd, dcr 0 1 0 1 pdr 01 01 010 1 cmos buffer pmos on on nmos on on pull-up mos on on note: ?indicates off status.
hd404639r series 43 mis3 input control signal v cc pull-up mos dcd, dcr pdr input data v cc hlt pull-up control signal buffer control signal output data d 4 ? 11 , r port figure 27-1 i/o buffer configuration (with pull-up mos) table 21-2 programmable i/o circuits (with pull-down mos) mis3 (bit 3 of mis) 0 1 dcd, dcr 0 1 0 1 pdr 01 01 010 1 cmos buffer pmos on on nmos on on pull-down mos on on note: ?indicates off status.
hd404639r series 44 v cc pdr pull-down control signal pull-down mos buffer control signal output data d 0 ? 3 port mis3 hlt input control signal input data dcd figure 27-2 i/o buffer configuration (with pull-down mos)
hd404639r series 45 table 22 circuit configurations of i/o pins i/o pin type circuit pins input/output pins v cc v cc pull-up control signal buffer control signal output data input data hlt mis3 dcd, dcr pdr input control signal d 4 ? 11 , r0 0 ?0 3 r1 0 ?1 3, r2 0 ?2 3 r3 0 ?3 3, r4 0 ?4 2 r5 0 ?5 2 r6 0 ?6 3 r7 0 ?7 3, r8 0 ?8 3 r9 0 ?9 3, ra 0 ?a 3 rb 0 ?b 3, rc 0 dcd pdr pull-down control signal buffer control signal output data mis3 hlt input data input control signal v cc d 0 ? 3 v cc v cc pull-up control signal buffer control signal output data input data hlt mis3 dcr pdr input control signal mis2, sm2b2 r4 3, r5 3 input pins input data input control signal d 12 , d 13 rd 0 ?d 3 , re 0
hd404639r series 46 i/o pin type circuit pins peripheral function pins input/ output pins v cc v cc pull-up control signal output data input data hlt mis3 sck 1 , sck 2 sck 1 , sck 2 sck 1, sck 2 peripheral function pins output pins v cc v cc pull-up control signal pmos control signal output data hlt mis3 so 1 , so 2 mis2, sm2b2 so 1 , so 2 v cc v cc pull-up control signal output data hlt mis3 tob, toc, tod tob, toc, tod input pins v cc input data hlt mis3 si 1 , si 2 , int 1 , etc pdr si 1 , si 2 , int 1 , int 2 , int 3 , int 4 , evnb , evnd int 0 , stopc input data int 0 , stopc notes: 1. the mcu is reset in stop mode, and peripheral function selection is cancelled. the hlt signal becomes low, and input/output pins enter high-impedance state. 2. the hlt signal is 1 in watch and subactive modes. d port (d 0 ? 13 ): consist of 12 input/output pins and 2 input pins addressed by one bit. d 0 ? 3 are high- current sources, d 4 ? 11 are high-current sinks, and d 12 and d 13 are input-only pins. pins d 0 ? 11 are set by the sed and sedd instructions, and reset by the red and redd instructions. output data is stored in the port data register (pdr) for each pin. all pins d 0 ? 13 are tested by the td and tdd instructions. the on/off statuses of the output buffers are controlled by d-port data control registers (dcd0?cd2: $02c?02e) that are mapped to memory addresses (figure 28).
hd404639r series 47 pins d 12 and d 13 are multiplexed with peripheral function pins stopc and i nt 0 , respectively. the peripheral function modes of these pins are selected by bits 2 and 3 (pmrc2, pmrc3) of port mode register c (pmrc: $025) (figure 29). r ports (r0 0 ?c 0 , rd 0 ?e 0 ): 49 input/output pins and 5 input pins addressed in 4-bit units. data is input to these ports by the lar and lbr instructions, and output from them by the lra and lrb instructions. output data is stored in the port data register (pdr) for each pin. the on/off statuses of the output buffers of the r ports are controlled by r-port data control registers (dcr0?crc: $030?03c) that are mapped to memory addresses (figure 28). pins r0 0 ?0 3 are multiplexed with peripheral pins i nt 1 ?nt 4 , respectively. the peripheral function modes of these pins are selected by bits 0? (pmrb0?mrb3) of port mode register b (pmrb: $024) (figure 30). pins r3 0 ?3 2 are multiplexed with peripheral pins tob, toc, and tod, respectively. the peripheral function modes of these pins are selected by bits 0 and 1 (tmb20, tmb21) of timer mode register b2 (tmb2: $013), bits 0? (tmc20?mc22) of timer mode register c2 (tmc2: $014), and bits 0? (tmd20?md23) of timer mode register d2 (tmd2: $015) (figures 31, 32, and 33). pins r3 3 and r4 0 are multiplexed with peripheral pins evnb and evnd, respectively. the peripheral function modes of these pins are selected by bits 0 and 1 (pmrc0, pmrc1) of port mode register c (pmrc: $025) (figure 29). pins r4 1 ?4 3 are multiplexed with peripheral pins sck 1 , si 1 , and so 1 , respectively. the peripheral function modes of these pins are selected by bit 3 (sm1a3) of serial mode register 1a (sm1a: $005), and bits 0 and 1 (pmra0, pmra1) of port mode register a (pmra: $004), as shown in figures 34 and 36. ports r5 1 ?5 3 are multiplexed with peripheral function pins sck 2 , si 2 , so 2 , respectively. the function modes of these pins can be selected by individual pins, by setting bit 3 (sm2a3) of serial mode register 2a (sm2a: $01b), and bits 2 and 3 (pmra2, pmra3) of port mode register a (pmra: $004) (figures 35 and 36). ports rd 0 ?d 3 are multiplexed with peripheral function pins comp 0 ?omp 3 , respectively. the function modes of these pins are selected by bit 3 (cer3) of the compare enable register (cer: $018). port re 0 is multiplexed with peripheral function pin vc ref . while functioning as vc ref , do not use this pin as an r port at the same time, otherwise, the mcu may malfunction. pull-up or pull-down mos transistor control: a program-controlled pull-up or pull-down mos transistor is provided for each input/output pin other than input-only pins d 12 and d 13 . the on/off status of all these transistors is controlled by bit 3 (mis3) of the miscellaneous register (mis: $00c), and the on/off status of an individual transistor can also be controlled by the port data register (pdr) of the corresponding pin?nabling on/off control of that pin alone (table 21 and figure 38). the on/off status of each transistor and the peripheral function mode of each pin can be set independently. how to deal with unused i/o pins: i/o pins that are not needed by the user system (floating) must be connected to v cc to prevent lsi malfunctions due to noise. these pins must either be pulled up to v cc by their pull-up mos transistors or by resistors of about 100 k w or pulled down to gnd by their pull-down mos transistors.
hd404639r series 48 bit initial value read/write bit name 3 0 w 2 0 w 0 0 w 1 0 w dcd0 to dcd2 data control register (dcd0 to 2: $02c to $02e) (dcr0 to c: $030 to $03c) bit initial value read/write bit name 0 0 w dcrc0 1 not used dcrc bit initial value read/write bit name correspondence between ports and dcd/dcr bits 3 0 w dcr03 register name dcd0 dcd1 dcd2 dcr0 dcr1 dcr2 dcr3 dcr4 dcr5 dcr6 dcr7 dcr8 dcr9 dcra dcrb dcrc bit 3 d 3 d 7 d 11 r0 3 r1 3 r2 3 r3 3 r4 3 r5 3 r6 3 r7 3 r8 3 r9 3 ra 3 rb 3 bit 2 d 2 d 6 d 10 r0 2 r1 2 r2 2 r3 2 r4 2 r5 2 r6 2 r7 2 r8 2 r9 2 ra 2 rb 2 bit 1 d 1 d 5 d 9 r0 1 r1 1 r2 1 r3 1 r4 1 r5 1 r6 1 r7 1 r8 1 r9 1 ra 1 rb 1 bit 0 d 0 d 4 d 8 r0 0 r1 0 r2 0 r3 0 r4 0 r5 0 r6 0 r7 0 r8 0 r9 0 ra 0 rb 0 rc 0 2 0 w dcr02 0 0 w dcr00 1 0 w dcr01 dcr0 to dcrb dcrb3 dcrb2 dcrb0 dcrb1 3 not used 2 not used dcd03 dcd23 dcd02 dcd22 dcd01 dcd21 dcd00 dcd20 0 1 off (high-impedance) on all bits cmos buffer on/off selection figure 28 data control registers (dcd, dcr)
hd404639r series 49 bit initial value read/write bit name 3 0 w pmrc3 2 0 w pmrc2 0 0 w pmrc0 1 0 w pmrc1 port mode register c (pmrc: $025) pmrc0 0 1 r3 3 pmrc1 0 1 r4 0 /evnd mode selection r4 0 evnd r3 3 / evnb mode selection evnb pmrc2 0 1 d 12 stopc pmrc3 0 1 d 13 d 13 / int 0 mode selection int 0 d 12 / stopc mode selection note: pmrc2 is reset to 0 only by reset input. when stopc is input in stop mode, pmrc2 is not reset but retains its value. * figure 29 port mode register c (pmrc )
hd404639r series 50 bit initial value read/write bit name 3 0 w pmrb3 2 0 w pmrb2 0 0 w pmrb0 1 0 w pmrb1 pmrb1 0 1 r0 1 /int 2 mode selection r0 1 int 2 port mode register b (pmrb: $024) pmrb0 0 1 r0 0 / int 1 mode selection r0 0 int 1 pmrb2 0 1 r0 2 /int 3 mode selection r0 2 int 3 pmrb3 0 1 r0 3 /int 4 mode selection r0 3 int 4 figure 30 port mode register b (pmrb) bit initial value read/write bit name 3 not used 2 not used 0 0 r/w tmb20 1 0 r/w tmb21 timer mode register b2 (tmb2: $013) tmb21 0 1 tmb20 0 1 0 1 r3 0 /tob mode selection r3 0 tob tob tob r3 0 port toggle output 0 output 1 output figure 31 timer mode register b2 (tmb2)
hd404639r series 51 bit initial value read/write bit name 3 not used 2 0 r/w tmc22 0 0 r/w tmc20 1 0 r/w tmc21 timer mode register c2 (tmc2: $014) tmc22 tmc20 0 1 0 1 0 1 0 1 tmc21 0 1 0 1 0 1 r3 1 /toc mode selection r3 1 toc toc toc toc toc toc toc r3 1 port toggle output 0 output 1 output inhibited pwm output figure 32 timer mode register c2 (tmc2)
hd404639r series 52 bit initial value read/write bit name 3 0 r/w tmd23 2 0 r/w tmd22 0 0 r/w tmd20 1 0 r/w tmd21 timer mode register d2 (tmd2: $015) tmd22 tmd20 0 1 0 1 0 1 0 1 tmd21 0 1 0 1 0 1 r3 2 /tod mode selection r3 2 tod tod tod tod tod tod tod r3 2 r3 2 port toggle output 0 output 1 output inhibited pwm output input capture (r3 2 port) tmd23 0 1 don? care don? care don? care figure 33 timer mode register d2 (tmd2)
hd404639r series 53 bit initial value read/write bit name 3 0 w sm1a3 2 0 w sm1a2 0 0 w sm1a0 1 0 w sm1a1 serial mode register 1a (sm1a: $005) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 output output output output output output output input prescaler prescaler prescaler prescaler prescaler prescaler system clock external clock ? 2048 ? 512 ? 128 ? 32 ? 8 ? 2 prescaler division ratio sm1a2 sm1a0 sm1a1 clock source sm1a3 0 1 r4 1 / sck 1 mode selection sck 1 r4 1 sck 1 figure 34 serial mode register 1a (sm1a)
hd404639r series 54 bit initial value read/write bit name 3 0 w sm2a3 2 0 w sm2a2 0 0 w sm2a0 1 0 w sm2a1 serial mode register 2a (sm2a: $01b) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 output output output output output output output input prescaler prescaler prescaler prescaler prescaler prescaler system clock external clock ? 2048 ? 512 ? 128 ? 32 ? 8 ? 2 prescaler division ratio sm2a2 sm2a0 sm2a1 clock source sm2a3 0 1 r5 1 / sck 2 mode selection sck 2 r5 1 sck 2 figure 35 serial mode register 2a (sm2a)
hd404639r series 55 pmra0 0 1 r4 3 /so 1 mode selection r4 3 so 1 bit initial value read/write bit name 3 0 w pmra3 2 0 w pmra2 0 0 w pmra0 1 0 w pmra1 port mode register a (pmra: $004) pmra2 0 1 r5 3 /so 2 mode selection r5 3 so 2 pmra3 0 1 r5 2 /si 2 mode selection r5 2 si 2 pmra1 0 1 r4 2 /si 1 mode selection r4 2 si 1 figure 36 port mode register a (pmra)
hd404639r series 56 bit initial value read/write bit name 3 0 w cer3 2 0 w cer2 0 0 w cer0 1 0 w cer1 compare enable register (cer: $018) cer1 0 0 1 1 analog input pin selection comp comp comp comp cer3 digital input mode: rd /comp ?d /comp operate as an r port. digital/analog selection analog input mode: rd /comp ?d /comp operate as analog input. 0 1 cer0 0 1 0 1 cer2 0 1 reference voltage selection external input voltage internal voltage 03 03 03 03 0 1 2 3 figure 37 compare enable register (cer) bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 mis2 pmos transistor on/off selection for pin r4 3 /so 1 miscellaneous register (mis: $00c) 0 1 on off refer to figure 18 in the operation modes section. t rc selection. mis3 0 1 pull-up and pull-down mos on/off selection off on mis1 mis0 figure 38 miscellaneous register (mis)
hd404639r series 57 prescalers the mcu has the following two prescalers, s and w. the prescalers operating conditions are listed in table 23, and the prescalers output supply is shown in figure 39. the timers a? input clocks except external events and the serial transmit clock except the external clock are selected from the prescaler outputs, depending on corresponding mode registers. prescaler operation prescaler s: 11-bit counter that inputs a system clock signal. after being reset to $000 by mcu reset, prescaler s divides the system clock. prescaler s keeps counting, except in watch and stop modes and at mcu reset. prescaler w: five-bit counter that inputs the x1 input clock signal (32-khz crystal oscillation) divided by eight. after being reset to $00 by mcu reset, prescaler w divides the input clock. prescaler w can be reset by software. table 23 prescaler operating conditions prescaler input clock reset conditions stop conditions prescaler s system clock (in active and standby mode), subsystem clock (in subactive mode) mcu reset mcu reset, stop mode, watch mode prescaler w 32-khz crystal oscillation mcu reset, software mcu reset, stop mode subsystem clock prescaler w system clock prescaler s clock selector timer a timer b timer c timer d serial interface 1 serial interface 2 f x /8 f x /4 or f x /8 figure 39 prescaler output supply
hd404639r series 58 timers the mcu has four timer/counters (a to d). timer a: free-running timer timer b: multifunction timer timer c: multifunction timer timer d: multifunction timer timer a is an 8-bit free-running timer. timers b? are 8-bit multifunction timers, whose functions are listed in table 24. the operating modes are selected by software. table 24 timer functions functions timer a timer b timer c timer d clock source prescaler s available available available available prescaler w available external event available available timer functions free-running available available available available time-base available event counter available available reload available available available watchdog available input capture available timer outputs toggle available available available 0 output available available available 1 output available available available pwm available available note: ?means not available. timer a timer a functions: timer a has the following functions. free-running timer clock time-base the block diagram of timer a is shown in figure 40.
hd404639r series 59 1/4 1/2 32.768-khz oscillator system clock prescaler w (psw) selector selector prescaler s (pss) selector internal data bus timer a interrupt request flag (ifta) clock overflow timer counter a (tca) timer mode register a (tma) 3 2 f 1/2 t wcyc f t wcyc per 2 4 8 32 128 512 1024 2048 ? ? ? ? ? ? ? ? 2 8 16 32 ? ? ? ? w w figure 40 block diagram of timer a timer a operations: free-running timer operation: the input clock for timer a is selected by timer mode register a (tma: $008). timer a is reset to $00 by mcu reset and incremented at each input clock. if an input clock is applied to timer a after it has reached $ff, an overflow is generated, and timer a is reset to $00. the overflow sets the timer a interrupt request flag (ifta: $001, bit 2). timer a continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. clock time-base operation: timer a is used as a clock time-base by setting bit 3 (tma3) of timer mode register a (tma: $008) to 1. the prescaler w output is applied to timer a, and timer a generates interrupts at the correct timing based on the 32.768-khz crystal oscillation. in this case, prescaler w and timer a can be reset to $00 by software. registers for timer a operation: timer a operating modes are set by the following registers. timer mode register a (tma: $008): four-bit write-only register that selects timer a? operating mode and input clock source as shown in figure 41.
hd404639r series 60 bit initial value read/write bit name 3 0 w tma3 2 0 w tma2 0 0 w tma0 1 0 w tma1 timer mode register a (tma: $008) 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 pss pss pss pss pss pss pss pss psw psw psw psw psw operating mode timer a mode tma3 tma1 tma2 tma0 source prescaler 2048t cyc 1024t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc input clock frequency 0 1 1 32t wcyc 16t wcyc 8t wcyc 2t wcyc 1/2t wcyc time-base mode 0 0 1 1 0 1 1 inhibited psw and tca reset don? care notes: 1. 2. 3. t wcyc = 244.14 m s (when a 32.768-khz crystal oscillator is used) timer counter overflow output period (seconds) = input clock period (seconds) 256. the division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. figure 41 timer mode register a (tma)
hd404639r series 61 timer b timer b functions : timer b has the following functions. free-running/reload timer external event counter timer output operation (toggle, 0, and 1 outputs) the block diagram of timer b is shown in figure 42. system clock evnb tob timer output control selector prescaler s (pss) clock timer read register bu (trbu) timer read register bl (trbl) timer counter b (tcb) timer write register bu (twbu) timer write register bl (twbl) timer mode register b1 (tmb1) timer mode register b2 (tmb2) timer b interrupt request flag (iftb) per 3 2 internal data bus 2 4 8 32 128 512 2048 ? ? ? ? ? ? ? free-running/ reload control overflow timer output control logic figure 42 block diagram of timer b
hd404639r series 62 timer b operations: free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register b1 (tmb1: $009). timer b is initialized to the value set in timer write register b (twbl: $00a, twbu: $00b) by software and incremented by one at each clock input. if an input clock is applied to timer b after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer b is initialized to its initial value set in timer write register b; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. the overflow sets the timer b interrupt request flag (iftb: $002, bit 0). iftb is reset by software or mcu reset. refer to figure 3 and table 1 for details. external event counter operation: timer b is used as an external event counter by selecting external event input as the input clock source. in this case, pin r3 3 / evnb must be set to evnb by port mode register c (pmrc: $025). timer b is incremented by one at each falling edge of signals input to pin evnb . the other operations are basically the same as the free-running/reload timer operation. timer output operation: the following three output modes can be selected for timer b by setting timer mode register b2 (tmb2: $013). toggle 0 output 1 output by selecting the timer output mode, pin r3 0 /tob is set to tob. the output from tob is reset low by mcu reset. ? toggle output: when toggle output mode is selected, the output level is inverted if a clock is input after timer b has reached $ff. by using this function and reload timer function, clock signals can be output at a required frequency for the buzzer. the output waveform is shown in figure 43. ? 0 output: when 0 output mode is selected, the output level is pulled low if a clock is input after timer b has reached $ff. note that this function must be used only when the output level is high. ? 1 output: when 1 output mode is selected, the output level is set high if a clock is input after timer b has reached $ff. note that this function must be used only when the output level is low.
hd404639r series 63 t (n + 1) t 256 t t (256 ?n) tmc13 = 0 the waveform is always fixed low when n = $ff. t: n: tmc13 = 1 input clock period to counter (figures 52 and 59) the value of the timer write register note: tmd13 = 0 tmd13 = 1 256 clock cycles 256 clock cycles free-running timer toggle output waveform (timers b, c, and d) pwm output waveform (timers c and d) (256 ?n) clock cycles (256 ?n) clock cycles reload timer figure 43 timer output waveform registers for timer b operation : by using the following registers, timer b operation modes are selected and the timer b count is read and written. timer mode register b1 (tmb1: $009) timer mode register b2 (tmb2: $013) timer write register b (twbl: $00a, twbu: $00b) timer read register b (trbl: $00a, trbu: $00b) port mode register c (pmrc: $025) timer mode register b1 (tmb1: $009): four-bit write-only register that selects the free- running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 44. it is reset to $0 by mcu reset.
hd404639r series 64 writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register b1 write instruction. setting timer b? initialization by writing to timer write register b (twbl: $00a, twbu: $00b) must be done after a mode change becomes valid. bit initial value read/write bit name 3 0 w tmb13 2 0 w tmb12 0 0 w tmb10 1 0 w tmb11 timer mode register b1 (tmb1: $009) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmb12 tmb10 tmb11 input clock period and input clock source r3 3 / evnb (external event input) tmb13 0 1 free-running/reload timer selection free-running timer reload timer figure 44 timer mode register b1 (tmb1) timer mode register b2 (tmb2: $013): two-bit read/write register that selects the timer b output mode as shown in figure 45. it is reset to $0 by mcu reset. bit initial value read/write bit name 3 not used 2 not used 0 0 r/w tmb20 1 0 r/w tmb21 timer mode register b2 (tmb2: $013) tmb21 0 1 tmb20 0 1 0 1 r3 0 /tob mode selection r3 0 tob tob tob r3 0 port toggle output 0 output 1 output figure 45 timer mode register b2 (tmb2)
hd404639r series 65 timer write register b (twbl: $00a, twbu: $00b): write-only register consisting of the lower digit (twbl) and the upper digit (twbu) as shown in figures 46 and 47. the lower digit is reset to $0 by mcu reset, but the upper digit value is invalid. timer b is initialized by writing to timer write register b. in this case, the lower digit (twbl) must be written to first, but writing only to the lower digit does not change the timer b value. timer b is initialized to the value in timer write register b at the same time the upper digit (twbu) is written to. when timer write register b is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer b. bit initial value read/write bit name 3 0 w twbl3 2 0 w twbl2 0 0 w twbl0 1 0 w twbl1 timer write register b (lower digit) (twbl: $00a) figure 46 timer write register b lower digit (twbl) bit initial value read/write bit name 3 undefined w twbu3 2 undefined w twbu2 0 undefined w twbu0 1 undefined w twbu1 timer write register b (upper digit) (twbu: $00b) figure 47 timer write register b upper digit (twbu) timer read register b (trbl: $00a, trbu: $00b): read-only register consisting of the lower digit (trbl) and the upper digit (trbu) that holds the count of the timer b upper digit (figures 48 and 49). the upper digit (trbu) must be read first. at this time, the count of the timer b upper digit is obtained, and the count of the timer b lower digit is latched to the lower digit (trbl). after this, by reading trbl, the count of timer b when trbu is read can be obtained. bit initial value read/write bit name 3 undefined r trbl3 2 undefined r trbl2 0 undefined r trbl0 1 undefined r trbl1 timer read register b (lower digit) (trbl: $00a) figure 48 timer read register b lower digit (trbl)
hd404639r series 66 bit initial value read/write bit name 3 undefined r trbu3 2 undefined r trbu2 0 undefined r trbu0 1 undefined r trbu1 timer read register b (upper digit) (trbu: $00b) figure 49 timer read register b upper digit (trbu) port mode register c (pmrc: $025): write-only register that selects r3 3 / evnb pin function as shown in figure 50. it is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 w pmrc3 2 0 w pmrc2 0 0 w pmrc0 1 0 w pmrc1 pmrc1 0 1 r4 0 /evnd mode selection r4 0 evnd port mode register c (pmrc: $025) pmrc0 0 1 r3 3 / evnb mode selection r3 3 evnb pmrc3 0 1 d 13 / int 0 mode selection d 13 int 0 pmrc2 0 1 d 12 / stopc mode selection d 12 stopc figure 50 port mode register c (pmrc)
hd404639r series 67 timer c timer c functions : timer c has the following functions. free-running/reload timer watchdog timer timer output operation (toggle, 0, 1, and pwm outputs) the block diagram of timer c is shown in figure 51. watchdog on flag (wdon) system reset signal timer c interrupt request flag (iftc) timer output control logic timer read register cu (trcu) timer output control timer read register cl (trcl) clock timer counter c (tcc) selector system clock prescaler s (pss) overflow internal data bus timer write register cu (twcu) timer write register cl (twcl) timer mode register c1 (tmc1) timer mode register c2 (tmc2) free-running /reload control watchdog timer control logic toc per 2 4 8 32 128 512 1024 2048 3 3 figure 51 block diagram of timer c
hd404639r series 68 timer c operations: free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register c1 (tmc1: $00d). timer c is initialized to the value set in timer write register c (twcl: $00e, twcu: $00f) by software and incremented by one at each clock input. if an input clock is applied to timer c after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer c is initialized to its initial value set in timer write register c; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. the overflow sets the timer c interrupt request flag (iftc: $002, bit 2). iftc is reset by software or mcu reset. refer to figure 3 and table 1 for details. watchdog timer operation: timer c is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (wdon: $020, bit 1) to 1. if a program routine runs out of control and an overflow is generated, the mcu is reset. program run can be controlled by initializing timer c by software before it reaches $ff. timer output operation: the following four output modes can be selected for timer c by setting timer mode register c2 (tmc2: $014). toggle 0 output 1 output pwm output by selecting the timer output mode, pin r3 1 /toc is set to toc. the output from toc is reset low by mcu reset. ? toggle output: the operation is basically the same as that of timer-b? toggle output. ? 0 output: the operation is basically the same as that of timer-b? 0 output. ? 1 output: the operation is basically the same as that of timer-b? 1 output. ? pwm output: when pwm output mode is selected, timer c provides the variable-duty pulse output function. the output waveform differs depending on the contents of timer mode register c1 (tmc1: $00d) and timer write register c (twcl: $00e, twcu: $00f). the output waveform is shown in figure 43. registers for timer c operation: by using the following registers, timer c operation modes are selected and the timer c count is read and written. timer mode register c1 (tmc1: $00d) timer mode register c2 (tmc2: $014) timer write register c (twcl: $00e, twcu: $00f) timer read register c (trcl: $00e, trcu: $00f)
hd404639r series 69 timer mode register c1 (tmc1: $00d): four-bit write-only register that selects the free- running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 52. it is reset to $0 by mcu reset. writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register c1 write instruction. setting timer c? initialization by writing to timer write register c (twcl: $00e, twcu: $00f) must be done after a mode change becomes valid. bit initial value read/write bit name 3 0 w tmc13 2 0 w tmc12 0 0 w tmc10 1 0 w tmc11 timer mode register c1 (tmc1: $00d) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 1024t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmc12 tmc10 tmc11 tmc13 0 1 free-running/reload timer selection free-running timer reload timer input clock period figure 52 timer mode register c1 (tmc1) timer mode register c2 (tmc2: $014): three-bit read/write register that selects the timer c output mode as shown in figure 53. it is reset to $0 by mcu reset.
hd404639r series 70 bit initial value read/write bit name 3 not used 2 0 r/w tmc22 0 0 r/w tmc20 1 0 r/w tmc21 timer mode register c2 (tmc2: $014) tmc22 0 tmc21 r3 1 /toc mode selection r3 1 toc toc toc toc toc toc toc r3 1 port toggle output 0 output 1 output inhibited pwm output tmc20 0 1 0 1 0 1 0 1 0 1 10 1 figure 53 timer mode register c2 (tmc2) timer write register c (twcl: $00e, twcu: $00f): write-only register consisting of a lower digit (twcl) and an upper digit (twcu) as shown in figures 54 and 55. the operation of timer write register c is basically the same as that of timer write register b (twbl: $00a, twbu: $00b). bit initial value read/write bit name 3 0 w twcl3 2 0 w twcl2 0 0 w twcl0 1 0 w twcl1 timer write register c (lower digit) (twcl: $00e) figure 54 timer write register c lower digit (twcl) bit initial value read/write bit name 3 undefined w twcu3 2 undefined w twcu2 0 undefined w twcu0 1 undefined w twcu1 timer write register c (upper digit) (twcu: $00f) figure 55 timer write register c upper digit (twcu)
hd404639r series 71 timer read register c (trcl: $00e, trcu: $00f): read-only register consisting of a lower digit (trcl) and an upper digit (trcu) that holds the count of the timer c upper digit as shown in figures 56 and 57. the operation of timer read register c is basically the same as that of timer read register b (trbl: $00a, trbu: $00b). bit initial value read/write bit name 3 undefined r trcl3 2 undefined r trcl2 0 undefined r trcl0 1 undefined r trcl1 timer read register c (lower digit) (trcl: $00e) figure 56 timer read register c lower digit (trcl) bit initial value read/write bit name 3 undefined r trcu3 2 undefined r trcu2 0 undefined r trcu0 1 undefined r trcu1 timer read register c (upper digit) (trcu: $00f) figure 57 timer read register c upper digit (trcu) timer d timer d functions: timer d has the following functions. free-running/reload timer external event counter timer output operation (toggle, 0, 1, and pwm outputs) input capture timer the block diagram for each operation mode of timer d is shown in figures 58 (a) and (b).
hd404639r series 72 timer d interrupt request flag (iftd) timer output control logic timer read register du (trdu) timer output control timer read register dl (trdl) clock timer counter d (tcd) selector system clock prescaler s (pss) overflow internal data bus timer write register du (twdu) timer write register dl (twdl) timer mode register d1 (tmd1) timer mode register d2 (tmd2) free-running/ reload control tod edge detection logic edge detection selection register 2 (esr2) edge detection control per 2 3 3 2 4 8 32 128 512 2048 evnd figure 58 (a) block diagram of timer d (free-running/reload timer)
hd404639r series 73 selector 2 4 8 32 128 512 2048 3 2 per input capture status flag (icsf) input capture error flag (icef) timer d interrupt request flag (iftd) error control logic edge detection logic timer read register du (trdu) timer read register dl (trdl) read signal clock timer counter d (tcd) overflow system clock edge detection control prescaler s (pss) input capture timer control timer mode register d1 (tmd1) timer mode register d2 (tmd2) edge detection selection register 2 (esr2) evnd internal data bus figure 58 (b) block diagram of timer d (input capture timer) timer d operations: free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register d1 (tmd1: $010).
hd404639r series 74 timer d is initialized to the value set in timer write register d (twdl: $011, twdu: $012) by software and incremented by one at each clock input. if an input clock is applied to timer d after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer d is initialized to its initial value set in timer write register d; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. the overflow sets the timer d interrupt request flag (iftd: $003, bit 0). iftd is reset by software or mcu reset. refer to figure 3 and table 1 for details. external event counter operation: timer d is used as an external event counter by selecting the external event input as an input clock source. in this case, pin r4 0 /evnd must be set to evnd by port mode register c (pmrc: $025). either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (esr2: $027). when both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. timer d is incremented by one at each detection edge selected by detection edge select register 2 (esr2: $027). the other operations are basi cally the same as the free-running/reload timer operation. timer output operation: the following four output modes can be selected for timer d by setting timer mode register d2 (tmd2: $015). toggle 0 output 1 output pwm output by selecting the timer output mode, pin r3 2 /tod is set to tod. the output from tod is reset low by mcu reset. ? toggle output: the operation is basically the same as that of timer-b? toggle output. ? 0 output: the operation is basically the same as that of timer-b? 0 output. ? 1 output: the operation is basically the same as that of timer-b? 1 output. ? pwm output: the operation is basically the same as that of timer-c? pwm output. input capture timer operation: the input capture timer counts the clock cycles between trigger edges input to pin evnd. either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (esr2: $027). when a trigger edge is input to evnd, the count of timer d is written to timer read register d (trdl: $011, trdu: $012), and the timer d interrupt request flag (iftd: $003, bit 0) and the input capture status flag (icsf: $021, bit 0) are set. timer d is reset to $00, and then incremented again. while icsf is set, if a trigger input edge is applied to timer d, or if timer d generates an overflow, the input capture error flag (icef: $021, bit 1) is set. icsf and icef are reset to 0 by mcu reset or by writing 0. by selecting the input capture operation, pin r3 2 /tod is set to r3 2 and timer d is reset to $00.
hd404639r series 75 registers for timer d operation: by using the following registers, timer d operation modes are selected and the timer d count is read and written. timer mode register d1 (tmd1: $010) timer mode register d2 (tmd2: $015) timer write register d (twdl: $011, twdu: $012) timer read register d (trdl: $011, trdu: $012) port mode register c (pmrc: $025) detection edge select register 2 (esr2: $027) timer mode register d1 (tmd1: $010): four-bit write-only register that selects the free- running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 59. it is reset to $0 by mcu reset. writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register d1 (tmd1: $010) write instruction. setting timer d? initialization by writing to timer write register d (twdl: $011, twdu: $012) must be done after a mode change becomes valid. when selecting the input capture timer operation, select the internal clock as the input clock source. bit initial value read/write bit name 3 0 w tmd13 2 0 w tmd12 0 0 w tmd10 1 0 w tmd11 timer mode register d1 (tmd1: $010) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmd12 tmd10 tmd11 input clock period and input clock source r4 0 /evnd (external event input) tmd13 0 1 free-running/reload timer selection free-running timer reload timer figure 59 timer mode register d1 (tmd1)
hd404639r series 76 timer mode register d2 (tmd2: $015): four-bit read/write register that selects the timer d output mode and input capture operation as shown in figure 60. it is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 r/w tmd23 2 0 r/w tmd22 0 0 r/w tmd20 1 0 r/w tmd21 timer mode register d2 (tmd2: $015) tmd22 tmd20 0 1 0 1 0 1 0 1 tmd21 0 1 0 1 0 1 r3 2 /tod mode selection r3 2 tod tod tod tod tod tod tod r3 2 r3 2 port toggle output 0 output 1 output inhibited pwm output input capture (r3 2 port) tmd23 0 1 don? care don? care don? care figure 60 timer mode register d2 (tmd2) timer write register d (twdl: $011, twdu: $012): write-only register consisting of a lower digit (twdl) and an upper digit (twdu) as shown in figures 61 and 62. the operation of timer write register d is basically the same as that of timer write register b (twbl: $00a, twbu: $00b). bit initial value read/write bit name 3 0 w twdl3 2 0 w twdl2 0 0 w twdl0 1 0 w twdl1 timer write register d (lower digit) (twdl: $011) figure 61 timer write register d lower digit (twdl)
hd404639r series 77 bit initial value read/write bit name 3 undefined w twdu3 2 undefined w twdu2 0 undefined w twdu0 1 undefined w twdu1 timer write register d (upper digit) (twdu: $012) figure 62 timer write register d upper digit (twdu) timer read register d (trdl: $011, trdu: $012): read-only register consisting of a lower digit (trdl) and an upper digit (trdu) as shown in figures 63 and 64. the operation of timer read register d is basically the same as that of timer read register b (trbl: $00a, trbu: $00b). when the input capture timer operation is selected and if the count of timer d is read after a trigger is input, either the lower or upper digit can be read first. bit initial value read/write bit name 3 undefined r trdl3 2 undefined r trdl2 0 undefined r trdl0 1 undefined r trdl1 timer read register d (lower digit) (trdl: $011) figure 63 timer read register d lower digit (trdl) bit initial value read/write bit name 3 undefined r trdu3 2 undefined r trdu2 0 undefined r trdu0 timer read register d (upper digit) (trdu: $012) 1 undefined r trdu1 figure 64 timer read register d upper digit (trdu) port mode register c (pmrc: $025): write-only register that selects r4 0 /evnd pin function as shown in figure 50. it is reset to $0 by mcu reset. detection edge select register 2 (esr2: $027): write-only register that selects the detection edge of signals input to pin evnd as shown in figure 65. it is reset to $0 by mcu reset.
hd404639r series 78 bit initial value read/write bit name 3 0 w esr23 2 0 w esr22 0 0 w 1 0 w esr21 detection edge selection register 2 (esr2: $027) esr23 0 1 esr22 0 1 0 1 evnd detection edge no detection falling-edge detection rising-edge detection double-edge detection note: both falling and rising edges are detected. esr20 * esr21 0 1 esr20 0 1 0 1 int detection edge no detection falling-edge detection rising-edge detection double-edge detection 4 * * figure 65 detection edge select register 2 (esr2) notes on use when using the timer output as pwm output, note the following point. from the update of the timer write register until the occurrence of the overflow interrupt, the pwm output differs from the period and duty settings, as shown in table 25. the pwm output should therefore not be used until after the overflow interrupt following the update of the timer write register. after the overflow, the pwm output will have the set period and duty cycle.
hd404639r series 79 table 25 pwm output following update of timer write register pwm output mode timer write register is updated during high pwm output timer write register is updated during low pwm output free running timer write register updated to value n interrupt request timer write register updated to value n interrupt request t (255 ?n) t (n + 1) t (n' + 1) t (255 ?n) t (n + 1) reload timer write register updated to value n interrupt request timer write register updated to value n interrupt request t t (255 ?n) t t t (255 ?n) t
hd404639r series 80 serial communications interface the mcu has two channels of serial interface. the transfer and receive start instructions differ according to the serial interface channel, but other functions are the same. the serial interface serially transfers or receives 8-bit data, and includes the following features. multiple transmit clock sources ? external clock ? internal prescaler output clock ? system clock output level control in idle states five registers, an octal counter, and a multiplexer are also configured for serial interfaces 1 and 2 as follows. serial interface 1 serial data register 1 (sr1l: $006, sr1u: $007) serial mode register 1a (sm1a: $005) serial mode register 1b (sm1b: $028) port mode register a (pmra: $004) miscellaneous register (mis: $00c) octal counter (oc1) selector serial interface 2 serial data register 2 (sr2l: $01d, sr2u: $01e) serial mode register 2a (sm2a: $01b) serial mode register 2b (sm2b: $01c) port mode register a (pmra: $004) octal counter (oc2) selector the block diagram of the serial interface is shown in figure 66.
hd404639r series 81 selector prescaler s (pss) 2 8 32 128 512 2048 selector i/o control logic idle control logic octal counter (oc1, oc2) serial interrupt request flag (ifs1, ifs2) clock serial data register (sr1l/u, sr2l/u) serial mode register 1a, 2a (sm1a, sm2a) serial mode register 1b, 2b (sm1b, sm2b) transfer control so , so sck , sck si , si system clock internal data bus 3 per 1/2 1/2 2 1 2 1 2 1 figure 66 block diagram of serial interface serial interface operation serial interface operation selecting and changing the operating mode: tables 26 (a) and 26 (b) list the serial interfaces operating modes. to select an operating mode, use one of these combinations of port mode register a (pmra: $004), serial mode register 1a (sm1a: $005), and serial mode register 2a (sm2a: $01b) settings; to change the operating mode of serial interface 1, always initialize the serial interface internally by writing data to serial mode register 1a; and to change the operating mode of serial interface 2, always initialize the serial interface internally by writing data to serial mode register 2a. note that serial interface
hd404639r series 82 1 is initialized by writing data to serial mode register 1a, and serial interface 2 is initialized by writing data to serial mode register 2a. refer to the following section registers for serial interface for details. pin setting: the r4 1 / sck 1 pin is controlled by writing data to serial mode register 1a (sm1a: $005). the r5 1 / sck 2 pin is controlled by writing data to serial mode register 2a (sm2a: $01b). pins r4 2 /si 1 , r4 3 /so 1 , r5 2 /si 2 , and r5 3 /so 2 are controlled by writing data to port mode register a (pmra: $004). refer to the following section registers for serial interface for details. transmit clock source setting: the transmit clock source of serial interface 1 is set by writing data to serial mode register 1a (sm1a: $005) and serial mode register 1b (sm1b: $028). the transmit clock source of serial interface 2 is set by writing data to serial mode register 2a (sm2a: $01b) and serial mode register 2b (sm2b: $01c). refer to the following section registers for serial interface for details. data setting: transmit data of serial interface 1 is set by writing data to serial data register 1 (sr1l: $006, sr1u: $007). transmit data of serial interface 2 is set by writing data to serial data register 2 (sr2l: $01d, sr2u: $01e). receive data of serial interface 1 is obtained by reading the contents of serial data register 1. receive data of serial interface 2 is obtained by reading the contents of serial data register 2. the serial data is shifted by each serial interface transmit clock and is input from or output to an external system. the output level of the so 1 and so 2 pins is invalid until the first data of each serial interface is output after mcu reset, or until the output level control in idle states is performed. transfer control: serial interface 1 is activated by the sts instruction. serial interface 2 is activated by a dummy read of serial mode register 2a (sm2a: $01b), which will be referred to as sm2a read. the octal counter is reset to 000 by the sts instruction (serial interface 2 is sm2a read), and it increments at the rising edge of the transmit clock for each serial interface. when the eighth transmit clock signal is input or when serial transmission/reception is discontinued, the octal counter is reset to 000, the serial interface 1 interrupt request flag (ifs1: $003, bit 2) for serial interface 1 and serial interface 2 interrupt request flag (ifs2: $023, bit 2) for serial interface 2 are set, and the transfer stops. when the prescaler output is selected as the transmit clock of serial interface 1, the transmit clock frequency is selected as 4t cyc to 8192t cyc by setting bits 0 to 2 (sm1a0?m1a2) of serial mode register 1a (sm1a: $005) and bit 0 (sm1b0) of serial mode register 1b (sm1b: $028) as listed in table 27. when the prescaler output is selected as the transmit clock of serial interface 2, the transmit clock frequency is selected as 4t cyc to 8192t cyc by setting bits 0 to 2 (sm2a0?m2a2) of serial mode register 2a (sm2a: $01b) and bit 0 (sm2b0) of serial mode register 2b (sm2b: $01c). note: to start serial interface 2, simply read serial mode register 2a by using the instruction that compares serial mode register 2a with the accumulator. serial mode register 2a is a read-only register, so $0 can be read.
hd404639r series 83 table 26 (a) serial interface 1 operating modes sm1a pmra bit 3 bit 1 bit 0 operating mode 1 0 0 continuous clock output mode 1 transmit mode 1 0 receive mode 1 transmit/receive mode table 26 (b) serial interface 2 operating modes sm2a pmra bit 3 bit 1 bit 0 operating mode 1 0 0 continuous clock output mode 1 transmit mode 1 0 receive mode 1 transmit/receive mode table 27 transmit clock (prescaler output) sm1b/ sm2b sm1a/ sm2a bit 0 bit 2 bit 1 bit 0 prescaler division ratio transmit clock frequency 0000 ? 2048 4096t cyc 1 ? 512 1024t cyc 10 ? 128 256t cyc 1 ? 32 64t cyc 100 ? 8 16t cyc 1 ? 24t cyc 1000 ? 4096 8192t cyc 1 ? 1024 2048t cyc 10 ? 256 512t cyc 1 ? 64 128t cyc 100 ? 16 32t cyc 1 ? 48t cyc
hd404639r series 84 operating states: serial interface 1 has the following operating states; transitions between them are shown in figure 67. sts wait state (serial interface 2 is in sm2a read wait state) transmit clock wait state transfer state continuous clock output state (only in internal clock mode) system reset 00 sm1a write 04 sts instruction 01 * transmit clock 02 eight transmit clock cycles sts instruction (ifs1 1) 03 05 ? sm1a write (ifs1 1) 06 ? sts instruction wait state (with octal counter = 000, transmit clock disabled) transmit clock wait state (octal counter = 000) transfer state (octal counter 000) * system reset 10 sm1a write 18 sm1a write 14 transmit clock 17 sts instruction 11 sts instruction (ifs1 1) 12 eight transmit clock cycles sts instruction (ifs1 1) 13 16 ? 15 ? * * transmit clock continuous output state (pmra 0, 1 = 00) transmit clock wait state (octal counter = 000) sts instruction wait state (with octal counter = 000, transmit clock disabled) transfer state (octal counter 000) note: internal clock mode external clock mode * for serial interface 2, this is accomplished by reading the sm2a register. circled numbers are referred to in the text. 1 1 transmit clock figure 67 serial interface state transition diagram the operation state of serial interface 2 is the same as serial interface 1 except that the sts instruction of serial interface 1 changes to sm2a read. the following shows the operation state of serial interface 1. sts wait state: the serial interface enters sts wait state by mcu reset (00, 10 in figure 67). in sts wait state, serial interface 1 is initialized and the transmit clock is ignored. if the sts instruction is then executed (01, 11), serial interface 1 enters transmit clock wait state.
hd404639r series 85 transmit clock wait state: transmit clock wait state is the period between the sts execution and the falling edge of the first transmit clock. in transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts serial data register 1 (sr1l: $006, sr1u: $007), and puts the serial interface in transfer state. however, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). the serial interface enters sts wait state by writing data to serial mode register 1a (sm1a: $005) (04, 14) in transmit clock wait state. transfer state: transfer state is the period between the falling edge of the first clock and the rising edge of the eighth clock. in transfer state, the input of eight clocks or the execution of the sts instruction sets the octal counter to 000, and the serial interface enters another state. when the sts instruction is executed (05, 15), transmit clock wait state is entered. when eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and sts wait state is entered (13) in internal clock mode. in internal clock mode, the transmit clock stops after outputting eight clocks. in transfer state, writing data to serial mode register 1a (sm1a: $005) (06, 16) initializes serial interface 1, and sts wait state is entered. if the state changes from transfer to another state, the serial 1 interrupt request flag (ifs1: $003, bit 2) is set by the octal counter that is reset to 000. continuous clock output state (only in internal clock mode): continuous clock output state is entered only in internal clock mode. in this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the sck 1 pin. when bits 0 and 1 (pmra0, pmra1) of port mode register a (pmra: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. if serial mode register 1a (sm1a: $005) is written to in continuous clock output mode (18), sts wait state is entered. output level control in idle states: when serial interface 1 is in sts instruction wait state and when serial interface 2 is in sm2a read wait state and transmit clock state, the output of each serial output pin, so 1 and so 2 , can be controlled by setting bit 1 (sm1b1) of serial mode register 1b (sm1b: $028) to 0 or 1, or bit 1 (sm2b1) of serial mode register 2b (sm2b: $01c) to 0 or 1. the output level control example of serial interface 1 is shown in figure 68. note that the output level cannot be controlled in transfer state.
hd404639r series 86 state mcu reset pmra write sm1a write sm1b write sr1l, sr1u write sts instruction sck 1 pin (input) so 1 pin ifs1 sts wait state transmit clock wait state transfer state transmit clock wait state sts wait state port selection external clock selection output level control in idle states dummy write for state transition output level control in idle states data write for transmission lsb msb flag reset at transfer completion external clock mode state mcu reset pmra write sm1a write sm1b write sr1l, sr1u write sts instruction sck 1 pin (output) so 1 pin ifs1 sts wait state transfer state transmit clock wait state sts wait state port selection internal clock selection output level control in idle states data write for transmission output level control in idle states lsb msb flag reset at transfer completion internal clock mode undefined undefined figure 68 example of serial interface 1 operation sequence
hd404639r series 87 transmit clock error detection (in external clock mode): each serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. a transmit clock error of this type can be detected as shown in figure 69. if more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial 1 interrupt request flag (ifs1: $003, bit 2) is set, and transmit clock wait state is entered. at the falling edge of the next normal clock signal, the transfer state is entered. after the transfer is completed and ifs1 is reset, writing to serial mode register 1a (sm1a: $005) changes the state from transfer to sts wait. at this time serial interface 1 is in the transfer state, and the serial 1 interrupt request flag is set again, and therefore the error can be detected. the same applies to serial interface 2.
hd404639r series 88 transfer completion (ifs1 1) interrupts inhibited ifs1 0 sm1a write ifs1 = 1 transmit clock error processing normal termination ? ? yes no transmit clock error detection flowchart transmit clock error detection procedures state transmit clock wait state transfer state transfer state transmit clock wait state noise transfer state has been entered by the transmit clock error. when sm1a is written,ifs1 is set. flag set because octal counter reaches 000. flag reset at transfer completion. sm1a write 12 3 45678 sck pin (input) ifs1 1 figure 69 transmit clock error detection
hd404639r series 89 notes on use: initialization after writing to registers: if port mode register a (pmra: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register 1a (sm1a: $005) and serial mode register 2a (sm2a: $01b) again. serial 1 interrupt request flag (ifs1: $003, bit 2) and serial 2 interrupt request flag (ifs2: $023, bit 2) set: for serial interface 1, if the state is changed from transfer state to another by writing to serial mode register 1a (sm1a: $005) or executing the sts instruction during the first low pulse of the transmit clock, the serial 1 interrupt request flag (ifs1: $003, bit 2) is not set. in the same way for serial interface 2, if the state is changed from transfer state to another by writing to serial mode register 2a (sm2a: $01b) or by executing the sts instruction during the first low pulse of the transmit clock, the serial 2 interrupt request flag is not set. to set the serial 1 interrupt request flag, a serial mode register 1a write or sts instruction execution must be programmed to be executed after confirming that the sck 1 pin is at 1, that is, after executing the input instruction to port r4. to set the serial 2 interrupt request flag, a serial mode register 2a write or sm2a instruction execution must be programmed to be executed after confirming that the sck 2 pin is at 1, that is, after executing the input instruction to port r5. registers for serial interface when serial interface operation is selected, serial data is read and written by the following registers. for serial interface 1 serial mode register 1a (sm1a: $005) serial mode register 1b (sm1b: $028) serial data register 1 (sr1l: $006, sr1u: $007) port mode register a (pmra: $004) miscellaneous register (mis: $00c) for serial interface 2 serial mode register 2a (sm2a: $01b) serial mode register 2b (sm2b: $01c) serial data register 2 (sr2l: $01d, sr2u: $01e) port mode register a (pmra: $004) serial mode register 1a (sm1a: $005): this register has the following functions (figure 70). r4 1 / sck 1 pin function selection serial interface 1 transmit clock selection serial interface 1 prescaler division ratio selection serial interface 1 initialization serial mode register 1a is a 4-bit write-only register. it is reset to $0 by mcu reset.
hd404639r series 90 a write signal input to serial mode register 1a discontinues the input of the transmit clock to serial data register 1 (sr1l: $006, sr1u: $007) and the octal counter, and the octal counter is reset to 000. therefore, if a write is performed during data transfer, the serial 1 interrupt request flag (ifs1: $003, bit 2) is set. written data is valid from the second instruction execution cycle after the write operation, so the sts instruction must be executed at least two cycles after that. bit initial value read/write bit name 3 0 w sm1a3 2 0 w sm1a2 0 0 w sm1a0 1 0 w sm1a1 serial mode register 1a (sm1a: $005) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 sm1a2 sm1a0 sm1a1 sm1a3 0 1 r4 1 / sck 1 mode selection r4 1 sck 1 sck 1 output output input clock source prescaler system clock external clock prescaler division ratio refer to table 27 figure 70 serial mode register 1a (sm1a) serial mode register 1b (sm1b: $028): this register has the following functions (figure 71). serial interface 1 prescaler division ratio selection serial interface 1 output level control in idle states serial mode register 1b (sm1b: $028) is a 2-bit write-only register. it cannot be written during data transfer. by setting bit 0 (sm1b0) of this register, the serial interface 1 prescaler division ratio is selected. only bit 0 (sm1b0) can be reset to 0 by mcu reset. by setting bit 1 (sm1b1), the output level of the so 1 pin is controlled in idle states of serial interface 1. the output level changes at the same time that sm1b1 is written to.
hd404639r series 91 bit initial value read/write bit name 3 not used 2 not used 0 0 w sm1b0 1 undefined w sm1b1 sm1b0 0 1 transmit clock division ratio prescaler output divided by 2 prescaler output divided by 4 serial mode register 1b (sm1b: $028) sm1b1 0 1 output level control in idle states low level high level figure 71 serial mode register 1b (sm1b) serial data register 1 (sr1l: $006, sr1u: $007): this register has the following functions (figures 72 and 73) serial interface 1 transmission data write and shift serial interface 1 receive data shift and read writing data in this register is output from the so 1 pin, lsb first, synchronously with the falling edge of the transmit clock; data is input, lsb first, through the si 1 pin at the rising edge of the transmit clock. input/output timing is shown in figure 74. data cannot be read or written during serial data transfer. if a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. bit initial value read/write bit name 3 undefined r/w sr13 2 undefined r/w sr12 0 undefined r/w sr10 1 undefined r/w sr11 serial data register 1 (lower digit) (sr1l: $006) figure 72 serial data register 1 (sr1l) bit initial value read/write bit name 3 undefined r/w sr17 2 undefined r/w sr16 0 undefined r/w sr14 1 undefined r/w sr15 serial data register 1 (upper digit) (sr1u: $007) figure 73 serial data register 1 (sr1u)
hd404639r series 92 lsb msb 12 345 678 transmit clock serial output data serial input data latch timing figure 74 serial interface output timing
hd404639r series 93 port mode register a (pmra: $004): this register has the following functions (figure 75). r4 2 /si 1 pin function selection r4 3 /so 1 pin function selection r5 2 /si 2 pin function selection r5 3 /so 2 pin function selection port mode register a (pmra: $004) is a 4-bit write-only register, and is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 w pmra3 2 0 w pmra2 0 0 w pmra0 1 0 w pmra1 port mode register a (pmra: $004) pmra2 0 1 r5 3 /so 2 mode selection r5 3 so 2 pmra3 0 1 r5 2 /si 2 mode selection r5 2 si 2 pmra0 0 1 r4 3 /so 1 mode selection r4 3 so 1 pmra1 0 1 r4 2 /si 1 mode selection r4 2 si 1 figure 75 port mode register a (pmra) miscellaneous register (mis: $00c): this register has the following functions (figure 76). r4 3 /so 1 pin pmos control miscellaneous register (mis: $00c) is a 4-bit write-only register and is reset to $0 by mcu reset.
hd404639r series 94 1 1 0 1 7.8125 ms 31.25 ms not used mis2 0 1 r4 3 /so 1 pmos on/off selection on off bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 miscellaneous register (mis: $00c) mis1 0 mis0 0 t rc 0.12207 ms 0.24414 ms * mis3 0 1 pull-up mos on/off selection off on note: * this value is valid only for direct transfer operation. figure 76 miscellaneous register (mis) serial mode register 2a (sm2a: $01b): this register has the following functions (figure 77). r5 1 / sck 2 pin function selection serial interface 2 transmit clock selection serial interface 2 prescaler division ratio selection serial interface 2 initialization serial mode register 2a (sm2a: $01b) is a 4-bit write-only register. it is reset to $0 by mcu reset. a write signal input to serial mode register 2a discontinues the input of the transmit clock to serial data register 2 (sr2l: $01d, sr2u: $01e) and the octal counter, and the octal counter is reset to 000. therefore, if a write is performed during data transfer, the serial 2 interrupt request flag (ifs2: $023, bit 2) is set. written data is valid from the second instruction execution cycle after the write operation, so the sm2a read instruction must be executed at least two cycles after that.
hd404639r series 95 bit initial value read/write bit name 3 0 w sm2a3 2 0 w sm2a2 0 0 w sm2a0 1 0 w sm2a1 serial mode register 2a (sm2a: $01b) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 sm2a2 sm2a0 sm2a1 sm2a3 0 1 r5 1 / sck 2 mode selection r5 1 sck 2 sck 2 output output input clock source prescaler system clock external clock prescaler division ratio refer to table 27 figure 77 serial mode register 2a (sm2a) serial mode register 2b (sm2b: $01c): this register has the following functions (figure 78). serial interface 2 prescaler division ratio selection serial interface 2 output level control in idle states r5 3 /so 2 pin pmos control serial mode register 2b is a 3-bit write-only register. it cannot be written during serial interface 2 data transfer. bit 0 (sm2b0) and bit 2 (sm2b2) are reset to $0 by mcu reset. by setting bit 0 (sm2b0) of this register, the serial interface 2 prescaler division ratio of serial interface 2 is selected. by resetting bit 1 (sm2b1), the output level of the so 2 pin is controlled in idle states of serial interface 2. the output level changes at the same time that sm2b1 is written to.
hd404639r series 96 bit initial value read/write bit name 3 not used 2 0 w sm2b2 0 0 w sm2b0 1 undefined w sm2b1 sm2b2 0 1 r5 /so pmos serial mode register 2b (sm2b: $01c) sm2b1 0 1 output level control in idle states low level high level sm2b0 0 1 transmit clock division ratio prescaler output divided by 2 prescaler output divided by 4 3 2 on off figure 78 serial mode register 2b (sm2b) serial data register 2 (sr2l: $01d, sr2u: $01e): this register has the following functions (figures 79 and 80). serial interface 2 transmission data write and shift serial interface 2 receive data shift and read writing data in this register is output from the so 2 pin, lsb first, synchronously with the falling edge of the transmit clock; data is input, lsb first, through the si 2 pin at the rising edge of the transmit clock. data cannot be read or written during serial data transfer. if a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. bit initial value read/write bit name 3 undefined r/w sr23 2 undefined r/w sr22 0 undefined r/w sr20 1 undefined r/w sr21 serial data register 2 (lower digit) (sr2l: $01d) figure 79 serial data register 2 (sr2l)
hd404639r series 97 bit initial value read/write bit name 3 undefined r/w sr27 2 undefined r/w sr26 0 undefined r/w sr24 1 undefined r/w sr25 serial data register 2 (upper digit) (sr2u: $01e) figure 80 serial data register 2 (sr2u)
hd404639r series 98 dtmf generator circuit the mcu provides a dual-tone multifrequency (dtmf) generator circuit. the dtmf signal consists of two sine waves to access the switching system. figure 81 shows the dtmf keypad and frequencies. each key enables tones to be generated corresponding to each frequency. figure 82 shows a block diagram of the dtmf circuit. the osc clock (400 khz, 800 khz, 2 mhz, 3.58 mhz, 4 mhz, 7.16 mhz or 8 mhz) is changed into six clock signals through the division circuit (1/2, 1/5, 1/9, 1/10, 1/18 and 1/20). the dtmf circuit uses one of the six clock signals, which is selected by system clock select register 1 (ssr1: $029) and system clock select register 2 (ssr2: $02a) depending on the osc clock frequency. the dtmf circuit has transformed programmable dividers, sine wave counters, and control registers. the dtmf generator circuit is controlled by the following three registers. 123a 456b 789c * 0# d r1 (697 hz) r2 (770 hz) r3 (852 hz) r4 (941 hz) c1 (1,209 hz) c2 (1,336 hz) c3 (1,477 hz) c4 (1,633 hz) figure 81 dtmf keypad and frequencies
hd404639r series 99 sine wave counter d/a transforma- tion program divider feedback sine wave counter d/a transforma- tion program divider feedback toner vt ref tonec toner output control tonec output control f osc tone generator control register (tgc) system clock selection register 1 (ssr1) system clock selection register 2 (ssr2) * 1 400 khz * 3 2 2 2 1 selector tone generator mode register (tgm) notes: 1. 2. 3. system clock selection register 2 (ssr2) is used to specify the divide-by-9 or divide-by-18 operation when a 3.58-mhz or 7.16 mhz system clock oscillator is used. applies to hd40a4638r, hd40a4639r and hd407a4639r. this is 397.8 khz when f osc is 3.58 mhz and 7.16 mhz. internal data bus 1/2 1/5 1/9 * 3 1/10 1/18 * 3 1/20 400 khz 800 khz 2 mhz 3.58 mhz 4 mhz 7.16 mhz * 2 8 mhz * 2 figure 82 block diagram of dtmf generator circuit
hd404639r series 100 tone generator mode register (tgm: $019): four-bit write-only register, which controls output frequencies as shown in figure 83, and is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 w tgm3 2 0 w tgm2 0 0 w tgm0 1 0 w tgm1 tone generator mode register (tgm: $019) tgm3 0 0 1 1 tgm2 0 1 0 1 tonec output frequencies f (1,209 hz) f (1,336 hz) f (1,477 hz) f (1,633 hz) c1 c2 c3 c4 tgm1 0 0 1 1 tgm0 0 1 0 1 toner output frequencies f (697 hz) f (770 hz) f (852 hz) f (941 hz) r1 r2 r3 r4 figure 83 tone generator mode register (tgm) tone generator control register (tgc: $01a): three-bit write-only register, which controls the start/stop of the dtmf signal output as shown in figure 84, and is reset to $0 by mcu reset. toner and tonec output can be independently controlled by bits 2 and 3 (tgc2, tgc3), and the dtmf circuit is controlled by bit 1 (tgc1) of this register. bit initial value read/write bit name 3 0 w tgc3 2 0 w tgc2 0 not used 1 0 w tgc1 tone generator control register (tgc: $01a) tgc1 0 1 dtmf enable bit dtmf disable dtmf enable tgc3 0 1 tonec output control (column) no output tonec output (active) tgc2 0 1 toner output control (row) no output toner output (active) figure 84 tone generator control register (tgc)
hd404639r series 101 system clock select registers 1 and 2 (ssr1: $029, ssr2: $02a): four-bit write-only registers. these registers must be set to the value specified in figures 85 and 86 depending on the frequency of the oscillator connected to the osc 1 and osc 2 pins. note that if the combination of the oscillation frequency and the values in these registers is different from that specified in figures 85 and 86, the dtmf output frequencies will differ from the correct frequencies as listed in table 28. bit initial value read/write bit name 3 0 w ssr13 2 0 w ssr12 0 0 w ssr10 1 0 w ssr11 system clock select register 1 (ssr1: $029) ssr13 0 1 32-khz oscillation stop oscillation operates in stop mode oscillation stops in stop mode ssr12 0 1 32-khz oscillation division ratio selection f = f /8 f = f /4 sub x sub x ssr22 0 1 0 1 400 khz 800 khz 2 mhz 4 mhz 3.58 mhz 8 mhz 7.16 mhz ssr11 0 1 don? care 1 don? care ssr10 0 1 0 1 don? care 1 don? care system clock selection ssr23 0 1 figure 85 system clock select register 1(ssr1)
hd404639r series 102 bit initial value read/write bit name 3 0 w ssr23 2 0 w ssr22 0 0 w ssr20 1 0 w ssr21 ssr22 0 serial clock select register 2 (ssr2: $02a) ssr21 0 1 system clock division ratio 1/4 division 1/8 division 1/16 division 1/32 division system clock selection selected from 400 khz, 800 khz, 2 mhz, 4 mhz 3.58 mhz 8 mhz 7.16 mhz ssr20 0 1 0 1 notes: * 1 * 1 1. refer to system clock select register 1 (ssr1) of figure 85. 2. the dtmf frequencies are not affected by the setting of the system clock division ratio. 1 0 1 ssr23 0 1 figure 86 system clock select register 2(ssr2) table 28 frequency deviation of the mcu from standard dtmf f osc = 400 khz, 800 khz, 2 mhz, 4 mhz, 8 mhz f osc = 3.58 mhz, 7.16 mhz standard dtmf (hz) mcu (hz) deviation from standard (%) mcu (hz) deviation from standard (%) r1 697 694.44 ?.37 690.58 ?.92 r2 770 769.23 ?.10 764.96 ?.65 r3 852 851.06 ?.11 846.33 ?.67 r4 941 938.97 ?.22 933.75 ?.77 c1 1,209 1,212.12 0.26 1,205.39 ?.30 c2 1,336 1,333.33 ?.20 1,325.92 ?.75 c3 1,477 1,481.48 0.30 1,473.25 ?.25 c4 1,633 1,639.34 0.39 1,630.23 ?.17 note: this frequency deviation value does not include the frequency deviation due to the oscillator element. also note that in this case the ratio of the high level and low level widths in the oscillator waveform due to the oscillator element will be 50%:50%.
hd404639r series 103 dtmf output: the sine waves of the row-group and column-group are individually converted in the d/a conversion circuit which provides a high-precision ladder resistance. the dtmf output pins (toner, tonec) transmit the sine waves of the row-group and column-group, respectively. figure 87 shows the tone output equivalent circuit. figure 88 shows the output waveform. one cycle of this wave consists of 32 slots. therefore, the output waveform is stable with little distortion. table 28 lists the frequency deviation of the mcu from standard dtmf signals. switch control vt gnd ref toner tonec figure 87 tone output equivalent circuit vt ref gnd time slots 1234567891011121314151617181920212223242526272829303132 figure 88 waveform of tone output
hd404639r series 104 comparator the block diagram of the comparator is shown in figure 89. the comparator compares input voltage with the reference voltage. internal voltage or external input voltage can be selected as the reference. internal reference voltage is selected from sixteen levels. setting bit 3 (cer3) of the compare enable register (cer: $018) to 1 executes a voltage comparison. when an input voltage at comp 0 ?omp 3 is higher than the reference voltage, the tm or tmd command sets the status flag (st) high for the corresponding bits of the compare data register (cdr: $017) to comp 0 ?omp 3 . on the other hand, when an input voltage at comp 0 ?omp 3 is lower, the tm or tmd command clears the st to 0. selector selector selector + 2 4 com- parator comparator data register (cdr) comparator enable register (cer) comparator control register (ccr) internal data bus comp 0 comp 1 comp 2 comp 3 vc ref 5r r r r 2r figure 89 block diagram of comparator compare enable register (cer: $018): four-bit write-only register which enables comparator operation, and selects the reference voltage and the analog input pin. compare control register (ccr: $016): four-bit write-only register which selects the internal reference voltage from sixteen levels. compare data register (cdr: $017): four-bit read-only register which latches the result of the comparison between the analog input pins and the reference voltage. bits 0 to 3 show the results of comparison with comp 0 ?omp 3 , respectively. this register can be read only by the tm or tmd
hd404639r series 105 command. only bit cer3 corresponds to the analog input pin selected with bits cer0 and cer1. after a compare operation, the data in this register is not retained. note on use: during the compare operation pins rd 0 /comp 0 ?d 3 /comp 3 operate as analog inputs and cannot operate as r ports. the comparator can operate in active mode and subactive mode but is disabled in other modes. the switch for the internal reference voltage is on only when the internal reference voltage is selected by cer2. re 0 /vc ref cannot operate as an r port when the external input voltage is selected as the reference. cer2 0 1 reference voltage selection external input voltage internal voltage bit initial value read/write bit name 3 0 w cer3 2 0 w cer2 0 0 w cer0 1 0 w cer1 compare enable register (cer: $018) cer3 0 digital/analog selection digital input mode: rd /comp 0 ?d /comp 3 operate as r port 03 1 analog input mode: rd /comp 0 ?d /comp 3 operate as analog input cer1 0 1 analog input pin selection comp 0 comp 1 comp 2 comp 3 cer0 0 1 0 1 03 figure 90 compare enable register (cer)
hd404639r series 106 bit initial value read/write bit name 3 0 w ccr3 2 0 w ccr2 0 0 w ccr0 1 0 w ccr1 compare control register (ccr: $016) ccr3 0 1 ccr1 0 1 0 1 0 1 0 1 ccr2 0 1 0 1 reference voltage selection 2/22 v 3/22 v 4/22 v 5/22 v 6/22 v 7/22 v 8/22 v 9/22 v 10/22 v 11/22 v 12/22 v 13/22 v 14/22 v 15/22 v 16/22 v 17/22 v ccr0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc figure 91 compare control register (ccr)
hd404639r series 107 bit initial value read/write bit name 3 r cdr3 2 r cdr2 0 r cdr0 1 r cdr1 compare data register (cdr: $017) undefined undefined undefined undefined result of comp 0 comparison result of comp 1 comparison result of comp 2 comparison result of comp 3 comparison figure 92 compare data register (cdr)
hd404639r series 108 programmable rom (hd407a4639r) the hd407a4639r is a ztat ? microcomputer with built-in prom that can be programmed in prom mode. prom mode pin description mcu mode prom mode mcu mode prom mode pin no. pin name i/o pin name i/o pin no. pin name i/o pin name i/o 1rd 0 /comp0 i 26 d 13 / int 0 iv pp 2rd 1 /comp1 i 27 r0 0 / int 1 i/o m 0 i 3rd 2 /comp2 i 28 r0 1 /int 2 i/o m 1 i 4rd 3 /comp3 i 29 r0 2 /int 3 i/o 5re 0 /vc ref i gnd 30 r0 3 /int 4 i/o 6 test i test i31 r1 0 i/o a 5 i 7 osc 1 iv cc 32 r1 1 i/o a 6 i 8 osc 2 o33r1 2 i/o a 7 i 9 reset i reset i 34 r1 3 i/o a 8 i 10 x1 i gnd 35 r2 0 i/o a 0 i 11 x2 o 36 r2 1 i/o a 10 i 12 gnd gnd 37 r2 2 i/o a 11 i 13 d 0 i/o ce i38 r2 3 i/o a 12 i 14 d 1 i/o oe i39 r3 0 /tob i/o 15 d 2 i/o v cc 40 r3 1 /toc i/o 16 d 3 i/o v cc 41 r3 2 /tod i/o 17 d 4 i/o 42 r3 3 / evnb i/o 18 d 5 i/o 43 r4 0 /evnd i/o 19 d 6 i/o 44 r4 1 / sck 1 i/o 20 d 7 i/o 45 r4 2 /si 1 i/o 21 d 8 i/o 46 r4 3 /so 1 i/o 22 d 9 i/o 47 r5 0 i/o 23 d 10 i/o a 13 i48 r5 1 / sck 2 i/o 24 d 11 i/o a 14 i49 r5 2 /si 2 i/o 25 d 12 / stopc ia 9 i50 r5 3 /so 2 i/o
hd404639r series 109 mcu mode prom mode mcu mode prom mode pin no. pin name i/o pin name i/o pin no. pin name i/o pin name i/o 51 r6 0 i/o a 1 i66 r9 3 i/o o 1 i/o 52 r6 1 i/o a 2 i67 ra 0 i/o o 0 i/o 53 r6 2 i/o a 3 i68 ra 1 i/o v cc 54 r6 3 i/o a 4 i69 ra 2 i/o 55 r7 0 i/o o 0 i/o 70 ra 3 i/o 56 r7 1 i/o o 1 i/o 71 rb 0 i/o 57 r7 2 i/o o 2 i/o 72 rb 1 i/o 58 r7 3 i/o o 3 i/o 73 rb 2 i/o 59 r8 0 i/o o 4 i/o 74 rb 3 i/o 60 r8 1 i/o o 5 i/o 75 rc 0 i/o 61 r8 2 i/o o 6 i/o 76 sel i 62 r8 3 i/o o 7 i/o 77 tonec o 63 r9 0 i/o o 4 i/o 78 toner o 64 r9 1 i/o o 3 i/o 79 v cc v cc 65 r9 2 i/o o 2 i/o 80 vt ref v cc notes: 1. i/o: input/output pin, i: input pin, o: output pin 2. each of o 0 ? 4 has two pins; before using, each pair must be connected together. programming the built-in prom the mcu? built-in prom is programmed in prom mode. prom mode is set by pulling test , m 0 , and m 1 low, and reset high as shown in figure 93. in prom mode, the mcu does not operate, but it can be programmed in the same way as any other commercial 27256-type eprom using a standard prom programmer and an 80-to-28-pin socket adapter. recommended prom programmers and socket adapters of the hd407a4639 are listed in table 30. since an hmcs400-series instruction is ten bits long, the hmcs400-series mcu has a built-in conversion circuit to enable the use of a general-purpose prom programmer. this circuit splits each instruction into five lower bits and five upper bits that are read from or written to consecutive addresses. this means that if, for example, 16 kwords of built-in prom are to be programmed by a general-purpose prom programmer, a 32-kbyte address space ($0000?7fff) must be specified. warnings 1. always specify addresses $0000 to $7fff when programming with a prom programmer. if address $8000 or higher is accessed, the prom may not be programmed or verified correctly. set all data in unused addresses to $ff. note that the plastic-package version cannot be erased or reprogrammed.
hd404639r series 110 2. make sure that the prom programmer, socket adapter, and lsi are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the lsi. before starting programming, make sure that the lsi is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. prom programmers have two voltages (v pp ): 12.5 v and 21 v. remember that ztat ? devices require a v pp of 12.5 v?he 21-v setting will damage them. 12.5 v is the intel 27256 setting. programming and verification the built-in prom of the mcu can be programmed at high speed without risk of voltage stress or damage to data reliability. programming and verification modes are selected as listed in table 29. table 29 prom mode selection pin mode ce oe v pp o 0 ? 7 programming low high v pp data input verification high low v pp data output programming inhibited high high v pp high impedance table 30 recommended prom programmers and socket adapters prom programmer socket adapter manufacturer model name package manufacturer model name data i/o corp. 121b fp-80b hitachi hs463esf01h aval corp. pkw-1000
hd404639r series 111 address a 0 to a 14 data o 0 to o 7 oe ce v cc v pp gnd v cc v cc o 0 to o 7 a 0 to a 14 oe ce v pp reset test m 0 m 1 v cc osc 1 d 2 d 3 ra 1 x1 hd407a4639r vt ref vc ref figure 93 prom mode connections
hd404639r series 112 addressing modes ram addressing modes the mcu has three ram addressing modes, as shown in figure 94 and described below. register indirect addressing mode: the contents of the w, x, and y registers (10 bits in total) are used as a ram address. when the area from $090 to $25f is used, a bank must be selected by the bank register (v: $03f). direct addressing mode: a direct addressing instruction consists of two words. the first word contains the opcode, and the contents of the second word (10 bits) are used as a ram address. memory register addressing mode: the memory registers (mr), which are located in 16 addresses from $040 to $04f, are accessed with the lamr and xmra instructions. ap 9 ap 0 w 1 y 0 w register x register y register ram address register direct addressing ap 9 ap 0 ram address direct addressing d 9 d 0 2nd word of instruction opcode 1st word of instruction ap 9 ap 0 ram address memory register addressing m 3 opcode instruction 000100 ap 8 ap 7 ap ap 5 ap 4 6 ap 3 ap 2 ap 1 ap ap ap ap ap ap ap ap 87654321 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 w 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 m 2 m 1 m 0 figure 94 ram addressing modes
hd404639r series 113 rom addressing modes and the p instruction the mcu has four rom addressing modes, as shown in figure 95 and described below. direct addressing mode: a program can branch to any address in the rom memory space by executing the jmpl, brl, or call instruction. each of these instructions replaces the 14 program counter bits (pc 13 ?c 0 ) with 14-bit immediate data. current page addressing mode: the mcu has 64 pages of rom with 256 words per page. a program can branch to any address in the current page by executing the br instruction. this instruction replaces the eight low-order bits of the program counter (pc 7 ?c 0 ) with eight-bit immediate data. if the br instruction is on a page boundary (address 256n + 255), executing that instruction transfers the pc contents to the next physical page, as shown in figure 97. this means that the execution of the br instruction on a page boundary will make the program branch to the next page. note that the hmcs400-series cross macroassembler has an automatic paging feature for rom pages. zero-page addressing mode: a program can branch to the zero-page subroutine area located at $0000 $003f by executing the cal instruction. when the cal instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (pc 5 ?c 0 ), and 0s are placed in the eight high- order bits (pc 13 ?c 6 ). table data addressing mode: a program can branch to an address determined by the contents of four- bit immediate data, the accumulator, and the b register by executing the tbr instruction. p instruction: rom data addressed in table data addressing mode can be referenced with the p instruction as shown in figure 96. if bit 8 of the rom data is 1, eight bits of rom data are written to the accumulator and the b register. if bit 9 is 1, eight bits of rom data are written to the r1 and r2 port output registers. if both bits 8 and 9 are 1, rom data is written to the accumulator and the b register, and also to the r1 and r2 port output registers at the same time. the p instruction has no effect on the program counter.
hd404639r series 114 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 2nd word of instruction opcode 1st word of instruction [jmpl] [brl] [call] pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc pc pc pc 10 11 12 13 program counter direct addressing zero page addressing d 5 d 4 d 3 d 2 d 1 d 0 instruction [cal] opcode pc 98 pc 76 pc 54 pc 3 pc 1 pc 0 pc pc 10 11 12 13 program counter 00 00 0 0 0 0 pc pc pc pc pc pc 2 b 1 b 0 a 3 a 2 a 1 a 0 accumulator program counter table data addressing pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc pc pc 10 11 12 13 b 2 b 3 b register p 3 p 0 [tbr] instruction opcode 0 0 p 2 p 1 pc opcode b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 instruction pc 90 pc pc pc 11 12 13 program counter current page addressing [br] pc 10 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc pc 8 pc p 0 p 1 p 2 p 3 figure 95 rom addressing modes
hd404639r series 115 b 1 b 0 a 3 a 2 a 1 a 0 accumulator referenced rom address address designation ra 9 ra 8 ra 7 ra 6 ra 5 ra 4 ra 3 ra 2 ra 1 ra 0 ra ra ra 10 11 12 13 b 2 b 3 b register 0 0 p 3 p 0 [p] instruction opcode p 2 p 1 ra ro 9 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 bbbb aa a a 3210 3210 if ro = 1 8 accumulator, b register rom data pattern output ro 9 rom data b 32103 210 if ro = 1 9 output registers r1, r2 bbbb bbb ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 figure 96 p instruction
hd404639r series 116 br aaa aaa nop 256 (n ?1) + 255 256n br aaa br bbb 256n + 254 256n + 255 256 (n + 1) bbb nop figure 97 branching when the branch destination is on a page boundary
hd404639r series 117 absolute maximum ratings item symbol value unit note supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +14.0 v 1 pin voltage v t ?.3 to v cc + 0.3 v total permissible input current ? i o 105 ma 2 total permissible output current ? i o 50 ma 3 maximum input current i o 4 ma 4, 5 30 ma 4, 6 maximum output current ? o 4 ma 7, 8 20 ma 7, 9 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +125 c notes: permanent damage may occur if these absolute maximum ratings are exceeded. normal operation must be under the conditions stated in the electrical characteristics tables. if these conditions are exceeded, the lsi may malfunction or its reliability may be affected. 1. applies to d 13 (v pp ) of hd407a4639r. 2. the total permissible input current is the total of input currents simultaneously flowing in from all the i/o pins to gnd. 3. the total permissible output current is the total of output currents simultaneously flowing out from v cc to all i/o pins. 4. the maximum input current is the maximum current flowing from each i/o pin to gnd. 5. applies to d 0 ? 3 , and r0?c. 6. applies to d 4 ? 11 . 7. the maximum output current is the maximum current flowing out from v cc to each i/o pin. 8. applies to d 4 ? 11 and r0?c. 9. applies to d 0 ? 3 .
hd404639r series 118 electrical characteristics dc characteristics (HD404638R, hd404639r, hd40a4638r, hd40a4639r: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c; hd407a4639r: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes input high voltage v ih reset, stopc , int 0 ?nt 4 , sck 1 si 1 , sck 2 , si 2 , evnb , evnd 0.9v cc ? cc + 0.3 v osc 1 v cc ?0.3 v cc + 0.3 v external clock input low voltage v il reset, stopc , int 0 ?nt 4 , sck 1 si 1 , sck 2 , si 2 , evnb , evnd ?.3 0.10 v cc v osc 1 ?.3 0.3 v external clock output high voltage v oh sck 1 , so 1 , sck 2 , so 2 , tob, toc, tod v cc ?1.0 v i oh = 0.5 ma output low voltage v ol sck 1 , so 1 , sck 2 , so 2 , tob, toc, tod 0.4 v i ol = 0.4 ma i/o leakage current | i il | reset, stopc , int 0 ?nt 4 , sck 1, si 1 , sck 2 , si 2 , so 1 , so 2 , evnb , evnd, osc 1 , tob, toc, tod 1 m av in = 0 v to v cc 1 current dissipation in active mode i cc1 v cc 2.5 5 ma v cc = 5 v, f osc = 4 mhz, digital input mode 2 i cc2 v cc 0.3 1.0 ma v cc = 3 v, f osc = 800 khz, digital input mode 2 i cc3 v cc ?9 mav cc = 5 v, f osc = 8 mhz, digital input mode 2, 8 i cmp1 v cc 6.5 9 ma v cc = 5 v, f osc = 4 mhz, analog comp. mode 3
hd404639r series 119 item symbol pin(s) min typ max unit test condition notes current dissipation in active mode i cmp2 v cc 2.8 3.5 ma v cc = 3 v, f osc = 800 khz, analog comp. mode 3 i cmp3 v cc 9 13 ma v cc = 5 v, f osc = 8 mhz, analog comp. mode 3, 8 current dissipation in standby mode i sby1 v cc 1.0 2 ma v cc = 5 v, f osc = 4 mhz 4 i sby2 v cc 0.1 0.3 ma v cc = 3 v, f osc = 800 khz 4 i sby3 v cc 2.0 4.0 ma v cc = 5 v, f osc = 8 mhz 4, 8 current dissipation in subactive mode i sub v cc ?835 m av cc = 3 v, 32 khz oscillator 5 current dissipation in watch mode i wtc v cc 4 7.5 m av cc = 3 v, 32 khz oscillator 5 current dissipation in stop mode i stop v cc 0.5 5 m av cc = 3 v, no 32 khz oscillator 5 stop mode retaining voltage v stop v cc 2 v no 32 khz oscillator 6 comparator input reference voltage scope vc ref vc ref 0v cc ?1.2 v allowable error of internal reference voltage v ofs ?00 100 mv v ofs = reference voltage ?vc ref 7 notes: 1. output buffer current is excluded. 2. i cc1 , i cc2 and i cc3 are the source currents when no i/o current is flowing while the mcu is in reset state. test conditions: mcu: reset pins: reset at v cc (v cc ?.3 to v cc ) test at v cc (v cc ?.3 to v cc )
hd404639r series 120 3. rd 0 ?d 3 pins are in analog input mode when no i/o current is flowing. test conditions: mcu: dtmf does not operate pins: rd 0 /comp 0 at gnd (0 v to 0.3 v) rd 1 /comp 1 at gnd (0 v to 0.3 v) rd 2 /comp 2 at gnd (0 v to 0.3 v) rd 3 /comp 3 at gnd (0 v to 0.3 v) re 0 /vc ref at gnd (0 v to 0.3 v) 4. i sby1 , i sby2 and i sby3 are the source currents when no i/o current is flowing while the mcu timer is operating. test conditions: mcu: i/o reset serial interface stopped dtmf does not operate standby mode pins: reset at gnd (0 v to 0.3 v) test at v cc (v cc ?.3 to v cc ) 5. these are the source currents when no i/o current is flowing. test conditions: pins: reset at gnd (0 v to 0.3 v) test at v cc (v cc ?.3 to v cc ) d 13 * at v cc (v cc ?.3 to v cc ) * applies to hd407a4639r. 6. ram data retention. 7. the reference voltage is the expected internal vc ref voltage selected by the compare control register (ccr: $016). example: when ccr = $2, reference voltage is 4/22 x v cc. 8. applies to hd40a4638r, hd40a4639r, hd407a4639r.
hd404639r series 121 i/o characteristics for standard pins (HD404638R, hd404639r, hd40a4638r, hd40a4639r: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c; hd407a4639r: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = 20 to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes input high voltage v ih d 12 ? 13 , r0?d, re 0 0.7 v cc ? cc + 0.3 v input low voltage v il d 12 ? 13 , r0?d, re 0 ?.3 0.3v cc v output high voltage v oh r0?c v cc ?.0 v i oh = 0.5 ma output low voltage v ol r0?c 0.4 v i ol = 0.4 ma i/o leakage current | i il | d 12 , r0?d re 0 , 1 m av in = 0 v to v cc 1 d 13 1 m av in = 0 v to v cc 1, 2 1 m av in = v cc ?0.3 v to v cc 1, 3 20 m av in = 0 v to 0.3 v 1, 3 pull-up mos current ? pu r0?c 5 30 90 m av cc = 3 v, v in = 0 v input high voltage v iha comp 0 comp 3 vc ref +0.1 v analog compare mode input low voltage v ila comp 0 comp 3 vc ref ?.1 v analog compare mode notes: 1. output buffer current is excluded. 2. applies to HD404638R, hd404639r, hd40a4638r and hd40a4639r. 3. apples to hd407a4639r.
hd404639r series 122 i/o characteristics for high-current pins (HD404638R, hd404639r, hd40a4638r, hd40a4639r: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c; hd407a4639r: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes input high voltage v ih d 0 ? 11 0.7 v cc ? cc + 0.3 v input low voltage v il d 0 ? 11 ?.3 0.3 v cc v output high voltage v oh d 0 ? 11 v cc ?1.0 v i oh = 0.5 ma, d 0 ? 3 2.0 v i oh = 10 ma, v cc = 4.5 v to 6.0 v 1 output low voltage v ol d 0 ? 11 0.4 v i ol = 0.4 ma d 4 ? 11 2.0 v i ol = 15 ma, v cc = 4.5 v to 6.0 v 1 i/o leakage current | i il | d 0 ? 11 1 m av in = 0 v to v cc 2 pull-up mos current ? pu d 4 ? 11 53090 m av cc = 3 v, v in = 0 v pull-down mos current i pd d 0 ? 3 53090 m av cc = 3 v, v in = 3 v notes: 1. hd407a4639r; v cc = 4.5 v to 5.5 v 2. output buffer current is excluded.
hd404639r series 123 dtmf characteristics (HD404638R, hd404639r, hd40a4638r, hd40a4639r: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c; hd407a4639r: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes tone output voltage (1) v or toner 500 660 mv rms vt ref ?gnd = 2.0 v, r l = 100 k w 1 tone output voltage (2) v oc tonec 520 690 mv rms vt ref ?gnd = 2.0 v, r l = 100 k w 1 tone output distortion %dis 3 7 % short circuit between toner and tonec r l = 100 k w 2 tone output ratio db cr 2.5 db short circuit between toner and tonec r l = 100 k w 2 notes: 400 khz, 800 khz, 2 mhz, 3.58 mhz, 4mhz, 7.16 mhz, or 8 mhz can be used as the operating trequency (f osc ). 1. see figure 98. 2. see figure 99.
hd404639r series 124 ac characteristics (HD404638R, hd404639r, hd40a4638r, hd40a4639r: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c; hd407a4639r: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes clock oscillation frequency f osc osc 1 , osc 2 400 khz 1 800 khz 1 2 mhz 1 3.58 mhz 1 4 mhz 1 7.16 mhz 1, 12 8 mhz 1, 12 x1, x2 32.768 khz instruction cycle time t cyc ? m sf osc = 4 mhz, 1/32 division 2 ? m sf osc = 4 mhz, 1/16 division 2 ? m sf osc = 4 mhz, 1/8 division 2 ? m sf osc = 4 mhz, 1/4 division 2 t subcyc 244.14 m s 32 khz oscillator, 1/8 division 3 122.07 m s 32 khz oscillator, 1/4 division 3 oscillation stabilization time (ceramic) t rc osc 1 , osc 2 7.5 ms 4, 5 oscillation stabilization time (crystal) t rc osc 1 , osc 2 40 ms v cc = 3.5 v to 6.0 v 4, 5, 6 60 ms 4, 5 x1, x2 3 s t a = ?0 c to +60 c4 external clock high width t cph osc 1 1100 ns f osc = 400 khz 7 550 ns f osc = 800 khz 7 215 ns f osc = 2 mhz 7 115 ns f osc = 3.58 mhz 7 105 ns f osc = 4 mhz 7 57.5 ns f osc = 7.16 mhz 7, 12 52.5 ns f osc = 8 mhz 7, 12
hd404639r series 125 item symbol pin(s) min typ max unit test condition notes external clock low width t cpl osc 1 1100 ns f osc = 400 khz 7 550 ns f osc = 800 khz 7 215 ns f osc = 2 mhz 7 115 ns f osc = 3.58 mhz 7 105 ns f osc = 4 mhz 7 57.5 ns f osc = 7.16 mhz 7, 12 52.5 ns f osc = 8 mhz 7, 12 external clock rise time t cpr osc 1 150 ns f osc = 400 khz 7 75 ns f osc = 800 khz 7 35 ns f osc = 2 mhz 7 25 ns f osc = 3.58 mhz 7 20 ns f osc = 4 mhz 7 12.5 ns f osc = 7.16 mhz 7, 12 10 ns f osc = 8 mhz 7, 12 external clock fall time t cpf osc 1 150 ns f osc = 400 khz 7 75 ns f osc = 800 khz 7 35 ns f osc = 2 mhz 7 25 ns f osc = 3.58 mhz 7 20 ns f osc = 4 mhz 7 12.5 ns f osc = 7.16 mhz 7, 12 10 ns f osc = 8 mhz 7, 12 int 0 ?nt 4 , evnb , evnd high width t ih int 0 int 4 , evnb , evnd 2 t cyc / t subcyc 8 int 0 ?nt 4 , evnb , evnd low width t il int 0 int 4 , evnb , evnd 2 t cyc / t subcyc 8 reset high width t rsth reset 2 t cyc 9 stopc low width t stpl stopc 1t rc 10 reset fall time t rstf reset 20 ms 9 stopc rise time t stpr stopc 20 ms 10
hd404639r series 126 item symbol pin(s) min typ max unit test condition notes input capacitance c in all pins except d 13 15 pf f = 1 mhz, v in = 0 v d 13 15 pf f = 1 mhz, v in = 0 v 13 d 13 180 pf f = 1 mhz, v in = 0 v 14 analog comparator stabilization time t cstb comp 0 comp 3 2t cyc 11 notes: except for the hd407a4639r, when v cc is between 2.2 v and 6.0 v, watch mode can be supported, and instruction execution is possible in active mode. 1. bits 0 and 1 (ssr10, ssr11) of system clock select register 1 (ssr1: $029) and bits 2 and 3 (ssr22, ssr23) of system clock select register 2 (ssr2: $02a) must be set according to the system clock frequency. 2. bits 0 and 1 (ssr20, ssr21) of system clock select register 2 (ssr2: $02a) must be set according to the division ratio of the system clock frequency. 3. bit 2 (ssr12) of system clock select register 1 (ssr1: $029) must be set according to the division ratio of the subsystem clock frequency. 4. the oscillation stabilization time is the period required for the oscillator to stabilize after v cc reaches 2.7 v at power-on, or after reset input goes high or stopc input goes low when stop mode is cancelled. at power-on or when stop mode is cancelled, reset or stopc must be input for at least t rc to ensure the oscillation stabilization time. if using a ceramic oscillator, contact its manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. set bits 0 and 1 (mis0, mis1) of the miscellaneous register (mis: $00c) according to the system oscillation of the oscillation stabilization time. 5. bits 0 and 1 (mis0, mis1) of the miscellaneous register (mis: $00c) must be set according to the oscillation stabilization time of the system clock oscillator. 6. hd407a4639r: v cc = 3.5 v to 5.5 v. 7. refer to figure 100. 8. refer to figure 101. the t cyc unit applies when the mcu is in standby or active mode. the t subcyc unit applies when the mcu is in watch or subactive mode. 9. refer to figure 102. 10. refer to figure 103. 11. analog comparator stabilization time is the period for the analog comparator to stabilize and for correct data to be read after entering rd 0 /comp 0 ?d 3 /comp 3 into analog input mode. 12. applies to hd40a4638r, hd40a4639r and hd407a4639r. hd40a4638r, hd40a4639r: v cc = 4.5 v to 6.0 v hd407a4639r: v cc = 4.5 v to 5.5 v 13. applies to HD404638R, hd404639r, hd40a4638r and hd40a4639r. 14. applies to hd407a4639r.
hd404639r series 127 serial interface timing characteristics (HD404638R, hd404639r, hd40a4638r, hd40a4639r: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 to +75 c; hd407a4639r: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 to +75 c, unless otherwise specified) during transmit clock output item symbol pin(s) test condition min typ max unit notes transmit clock cycle time t scyc sck 1, sck 2 load shown in figure 105 1 t cyc 1 transmit clock high width t sckh sck 1, sck 2 load shown in figure 105 0.5 t scyc 1 transmit clock low width t sckl sck 1, sck 2 load shown in figure 105 0.5 t scyc 1 transmit clock rise time t sckr sck 1, sck 2 load shown in figure 105 200 ns 1 transmit clock fall time t sckf sck 1, sck 2 load shown in figure 105 200 ns 1 serial output data delay time t dso so 1, so 2 load shown in figure 105 500 ns 1 serial input data setup time t ssi si 1, si 2 300 ns 1 serial input data hold time t hsi si 1, si 2 300 ns 1
hd404639r series 128 during transmit clock input item symbol pin(s) test condition min typ max unit notes transmit clock cycle time t scyc sck 1, sck 2 1 t cyc 1 transmit clock high width t sckh sck 1, sck 2 0.5 t scyc 1 transmit clock low width t sckl sck 1, sck 2 0.5 t scyc 1 transmit clock rise time t sckr sck 1, sck 2 200 ns 1 transmit clock fall time t sckf sck 1, sck 2 200 ns 1 serial output data delay time t dso so 1, so 2 load shown in figure 105 500 ns 1 serial input data setup time t ssi si 1, si 2 300 ns 1 serial input data hold time t hsi si 1, si 2 300 ns 1 note: 1. refer to figure 104. r = 100 k w l r = 100 k w l tonec toner gnd figure 98 tone output load circuit
hd404639r series 129 r = 100 k w l tonec toner gnd figure 99 distortion db cr load circuit t cpr t cpf v cc ?0.3 v 0.3 v t cph t cpl 1/f cp osc 1 figure 100 external clock timing 0.9 v cc 0.1 v cc int 0 ?nt 4 , evnb , evnd t ih t il figure 101 interrupt timing reset t rstf t rsth 0.9 v cc 0.1 v cc figure 102 reset timing
hd404639r series 130 t stpr t stpl 0.9 v cc 0.1 v cc stopc figure 103 stopc timing 0.9 v cc 0.1 v cc t dso t sckf t sckl t ssi t hsi t scyc t sckr 0.4 v v ?0.5 v cc v ?1.0 v (0.9 v ) cc 0.4 v (0.1 v ) sck sck so so si si note: * cc v ?1.0 v and 0.4 v are the threshold voltages for transmit clock output. cc cc t sckh * 1 2 1 2 1 2 cc 0.9 v and 0.1 v are the threshold voltages for transmit clock output. cc * figure 104 serial interface timing r l = 2.6 k w v cc 1s2074 h or equivalent r 12 k w test point c 30 pf figure 105 timing load circuit
hd404639r series 131 notes on rom out please pay attention to the following items regarding rom out. on rom out, fill the rom area indicated below with 1s to create the same data size as a 16-kword version (hd404639r, hd40a4639r). a 16-kword data size is required to change rom data to mask manufacturing data since the program used is for a 16-kword version. this limitation applies when using an eprom or a data base. vector address (16 words) zero-page subroutine (64 words) pattern & program (8,192 words) not used rom 8-kword version: HD404638R, hd40a4638r address $2000?3fff $0000 $000f $0010 $003f $0040 $1fff $2000 $3fff fill this area with 1s
hd404639r series 132 hd404638/hd404639/HD404638R/hd404639r/hd40a4638r/hd40a4639r option list 1. rom size please check off the appropriate applications and enter the necessary information. please specify the first type listed below (the upper bits and lower bits are mixed together) when using the eprom on-package microcomputer type (including ztat tm version). standaed version : hd404638 standard version : HD404638R high-speed version : hd40a4638r standard version : hd404639 standard version : hd404639r high-speed version : hd40a4639r rom 8-kword rom 16-kword date of order customer department name rom code name lsi number 2. optional functions note: * options marked with an asterisk require a subsystem crystal oscillator (x1, x2). * * * with 32-khz cpu operation, with time-base for clock without 32-khz cpu operation, with time-base for clock without 32-khz cpu operation, without time-base 4. oscillator for osc1 and osc2 ceramic oscillator crystal oscillator external clock f = f = f = mhz mhz mhz 3. rom code media eprom: the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu...). eprom: the upper bits and lower bits are separated. the upper bits and lower five bits are programmed to different eproms. 5. stop mode used not used 6. package fp-80b //
hd404639r series 133 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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